Latest threads in Field-Programmable Gate Arrays

Xilinx ISE 7.1i / stuck down XCR3064 outputs

Hi, I'm trying to use Xilinx ISE 7.1 on Linux to target an XCR3064. What seemed to happen was any pin configured as an...

6 21yrs

alex

6 21yrs alex

LVDS PCI card is needed

Hello, As a part of a project I am looking for a FPGA on PCI that has 8 LVDS channels and the driver of this card that...

8 21yrs

marcsok

8 21yrs marcsok

Modelsim simulations without ISE

I'm trying to do some simulations in modelsim that use one of the xilinx libraries (Specificially the RAMB4_S4_S4), but...

3 21yrs

arlencox

3 21yrs arlencox

Single Event Functional Interrupts (SEFI) in Virtex

Hello all, I am doing a literature survey on SEFIs in Xilinx FPGAs. Unfortunately, there are not many papers on this. I...

9 21yrs

sams235

9 21yrs sams235

How to use the library in VHDL (ISE)?

I add a library in my VHLD code(ISE 6.3 but the system tell me that "the library can't be found Thank

0 21yrs

Eaglet_Bff

0 21yrs Eaglet_Bff

Xilinx ISE Input Pins Problem

Hi All, I was wondering is there any way to synthesis a design of mine on an FPGA using the ISE tool so that I can get...

1 21yrs

keith.lumsden

1 21yrs keith.lumsden

VHDL to schematic conversion

Please mention a tool that can accepts VHDL code and converts it into a circuit schematic(preferably at the register tra...

3 21yrs

khansaca

3 21yrs khansaca

A "simple" problem...

Good morning, I'm a beginner with FPGA. I've recently built a simple board with one Spartan 3 FPGA, no configuration PR...

6 21yrs

enzo_br

6 21yrs enzo_br

HWICAP BRAM access (with EDK)

Hi, I am new to FPGA design and especially to Xilinx EDK. How does the HWICAP module (on Virtex-II and Virtex-II Pro) a...

1 21yrs

eem

1 21yrs eem

Spartan II/E Configuration readback

XAPP176 defines how to read back the configuration file but doesn't state whether this can be done while the device is o...

1 21yrs

CPLD: collapse

Hallo, in an CPLD-Design (XC95??XL), I have 2 data-strobe signals, and a data-stobe-select-signal. The selected strobe...

5 21yrs

post

5 21yrs post

Xilinx V2-Pro + Select Map programming

I've got a design using Select Map mode to program a Xilinx V2-Pro part. Many of the boards work, but one has stopped a...

6 21yrs

johnp3+nospam

6 21yrs johnp3+nospam

FPGA with 2 JTAG ports

Can an FPGA have two JTAG ports for programming an FPGA chip? One is conected thro XCf02s to the FPGA and the other is...

6 21yrs

fpgavhdl

6 21yrs fpgavhdl

EDK-Creating new peripheral

I am trying to connect a custom IP to my MicroBlaze design. This custom IP is connected to the OPB Bus. It reads data f...

3 21yrs

kittyawake

3 21yrs kittyawake

80x86 verilog (not complete!) sources released

http://gforge.openchip.org/projects/a86/ I had some working demos for ML300, but the project was iced oct'2004 the core...

2 21yrs

antti

2 21yrs antti

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