Sdram controller on the Altera Cyclone board!

Hi I wrote a sdram controller which has pass the RTL simulation. But when it come to the Altera cyclone board,the read/write data were wrong.I have written sdram with some data,and then I read the data from sdram.But found the data is not equal to what have been written into the sdram.One or Some bits have wrong.It is random bit error!I don't know what's wrong.About the clock? or board delay? or else?Please help me out! Thanks and Regards!

Reply to
kingkang
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Did you set up the right delay for the clock of the SDRAM ? I use a

288 deg phase shift on my pll to feed the SDRAM, at 50 MHz. It can be something else for you thought.

That's one of the most important thing.

Regards Nick

Reply to
Nick

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