Hi I wrote a sdram controller which has pass the RTL simulation. But when it come to the Altera cyclone board,the read/write data were wrong.I have written sdram with some data,and then I read the data from sdram.But found the data is not equal to what have been written into the sdram.One or Some bits have wrong.It is random bit error!I don't know what's wrong.About the clock? or board delay? or else?Please help me out! Thanks and Regards!
- posted
18 years ago