Hi Group, I am using SPARTAN3 CLBs to divide a clock. I can't use the DCM because the input clock is less than the minimum required by the DCM. Does anybody know how to calculate/estimate the jitter on the divided clock?
I am using the following VHDL code to divide by 2
div2: process wait until Clkin'event and Clkin = '1'; Clkdiv2