Clock Jitter on Xilinx FPGA

Hi Group, I am using SPARTAN3 CLBs to divide a clock. I can't use the DCM because the input clock is less than the minimum required by the DCM. Does anybody know how to calculate/estimate the jitter on the divided clock?

I am using the following VHDL code to divide by 2

div2: process wait until Clkin'event and Clkin = '1'; Clkdiv2

Reply to
Sudhir.Singh
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is your clock less than 1MHz? for S3 the minimum supported clock is 1MHz (DFS mode)

antti

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Reply to
Antti Lukats

Hi Antti, My clock frequency is 10.84MHz. I tried to use the CoreGen on Xilinx ISE to create the DCM component but it didn't let me. It gave a error message that the minimum clock frequency was something like 25MHz. Have you used the CoreGen or manually done DCM settings?

Thanks

Reply to
Sudhir.Singh

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you can not use CLK0 outputs must deselect all those, leaving FX only then you can use coregen for DCM input as low as 1MHz

antti

Reply to
Antti Lukats

Thank you Antii.

Reply to
Sudhir.Singh

because

clock?

Howdy Sudhir,

If you are truely concerned about jitter, using the DCM would not be the way to go, even if it did let you. The datasheet lists CLKOUT_PER_JIT for a DCM... it's lowest when using the CLK0 output, and highest when using the CLKFX output, where I don't recall ever seeing anything less than 600ps of jitter spec'ed:

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To minimize jitter, don't use a DLL/DCM, stay off the global clock lines, and keep the routing as short as possible within the device (put the output pin close to the input pin).

Good luck,

Marc

Reply to
Marc Randolph

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Are you serious? This just a plain 2:1 divider, more or less jitter free (yeah yeah, something in the 50 ps range maybe due to noise on VCC and other things that disturb the clock input) . Regards Falk

Reply to
Falk Brunner

At 184.5 ns per Unit Interval, what additive jitter do you consider "large" or "small?" If you are using the 5.42 MHz generated clock to produce a spectrally pure clock for an external device, just what *is* your sensitivity? Keep in mind that FPGAs are not precision analog components. The effect of nearby signals on the same I/O bank will be felt on the jitter of any clock that goes through that I/O bank. These effects are either insignificant or deadly depending on what you're doing with the "jitter."

Reply to
John_H

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