Field-Programmable Gate Arrays

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EDK 7.1, Virtex4 GPIO PULLIP problem

hi a quick question I have and microblaze in Virtex4 (EDK 7.1 SPx), the system has several GPIO instances it all works...
0 comments posted 20yrs
posted by antti
0 comments posted 20yrs posted by antti

Forcing carry-ripple adder ?

Hello, When implementing a 4 bits up/down counter on a Xilinx FPGA, the synthesis tool doesn't do it the "classic" way,...
8 comments posted 20yrs
posted by com.246tNt
8 comments posted 20yrs posted by com.246tNt

Installing FPGA Advantage on Linux machine

Does anyone know the process of installing FPGA Adv on Linux based system? Does FPGA Adv be have Linux support or not?...
3 comments posted 20yrs
posted by fahad.arif
3 comments posted 20yrs posted by fahad.arif

pci ml310 board

Hello, I am using xilinx ml310 board. Now I want to use networking feature on the board and hence I have to enable the...
5 comments posted 20yrs
posted by nitesh.guinde
5 comments posted 20yrs posted by nitesh.guinde

Wirelength information from Xilinx ISE 6.1

Hi, I am doing some experiments and I need to find out the total wirelength of my design. I am using Xilinx ISE 6.1 for...
1 comments posted 20yrs
posted by anup
1 comments posted 20yrs posted by anup

Bus for Spartan3

How could I implement a bus in my Spartan3 to let it communicate thorough a 16bit wide, 100MHz bus with a Blackfin DSP?...
4 comments posted 20yrs
posted by marco
4 comments posted 20yrs posted by marco

old xilinx components

Hello, What tools do I need for changing an outsourced dising from a 3020A to a 3030A Xilinx device (the 3020A is obsole...
8 comments posted 20yrs
posted by svhb
8 comments posted 20yrs posted by svhb

Internal signal to drive clock resources

Is it possible to drive global clock routing networks with an internal signal on a Virtex-E FPGA? I am trying to develo...
2 comments posted 20yrs
posted by aydin3w
2 comments posted 20yrs posted by aydin3w

8x8-bit multiply

Hello all I want to multiply two signed 8-bit numbers and pick 8 bits from the result. My code is like this: library IE...
1 comments posted 20yrs
posted by siba
1 comments posted 20yrs posted by siba

how to use registers and fifo in ipif

Hi all, I have created my own ip core by ise and the "create/import peripheral" function in edk. When I created the ip...
1 comments posted 20yrs
posted by lnzhao
1 comments posted 20yrs posted by lnzhao

PC Core AD(x) I/O Enable?

I notice that the Xilinx PCI32 core for Spartan 3 does not map the tristate enable FF's for the AD(x) lines to IOB's. I...
4 comments posted 20yrs
posted by
4 comments posted 20yrs posted by