Field-Programmable Gate Arrays

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To create an IPCORE

Hi, How can I create an IPCORE from my VHDL code. I want to be able to distribute my newly created block without given a...
1 comments posted 20yrs
posted by alonzo
1 comments posted 20yrs posted by alonzo

Delay insertion in Xilinx Verilog

Hello, I'm trying to force a long logic delay in a Xilinx FPGA using a chain of inverters. However, these seem to get o...
7 comments posted 20yrs
posted by anon
7 comments posted 20yrs posted by anon

Easy Xilinx Platform Studio Question

After clicking Applications and making active one, and only one, of the many software examples for the ml403_emb_ref_mb...
7 comments posted 20yrs
posted by bradsmallridge
7 comments posted 20yrs posted by bradsmallridge

looking for FPGA pin header board

Strange request but I'm looking for an fpga board that pretty much only has an fpga (perferably xilinx because i've onl...
7 comments posted 20yrs
posted by Terradestroyer
7 comments posted 20yrs posted by Terradestroyer

Verilog Editor.

Check out the Zeus Editor. www.zeusedit.com Is is very lost cost and now supports Verilog files with nice code folding!...
18 comments posted 20yrs
posted by emh203
18 comments posted 20yrs posted by emh203

ML402 DDR SDRAM

Has anyone been able to get the ML402's DDR SDRAM running with a MIG-generated DDR controller, as opposed to the EDK PL...
3 comments posted 20yrs
posted by jeredw
3 comments posted 20yrs posted by jeredw

XILINX ISE 7.1 Symbol Editor

Hello, is there any way to rotate a selected group in the Symbol Editor? Thanks and greetings Udo
0 comments posted 20yrs
posted by WeikEngOff
0 comments posted 20yrs posted by WeikEngOff

What does @ mean in EDIF?

Is it part of EDIF 2 0 0? A later version? I searched the 2 0 0 BNF on the EDIF website and didn't find it. Thanks!
0 comments posted 20yrs
posted by myusenetacct
0 comments posted 20yrs posted by myusenetacct

VHDL algorithm/code for implementing QAM on FPGA

Hello Everyone, I am working on designing a digital modulator that will implement QAM on FPGA. The FPGA will be program...
2 comments posted 20yrs
posted by profkwame
2 comments posted 20yrs posted by profkwame

BRAMs readback

Hi all. I'm using a Virtex2 fpga which uses a lot of BRAMs. The design modifies the content of these BRAMs during elabo...
5 comments posted 20yrs
posted by giohdl
5 comments posted 20yrs posted by giohdl

Xilinx Package/Logic Options

Hello: This is a question/comment for the Xilinx people here. Is there a technical (or Marketing) reason that there are...
4 comments posted 20yrs
posted by emh203
4 comments posted 20yrs posted by emh203

Malloc on PowerPC on VirtexII pro

hi, I'm using a PPC405 on a Virtex2 pro. I try to allocate memory with malloc() function. It compiles without any probl...
2 comments posted 20yrs
posted by tiboinsa
2 comments posted 20yrs posted by tiboinsa

Spartan3 bus for DSP

How could I implement a bus in my Spartan3 to let it communicate thorough a 16bit wide, 100MHz bus with a Blackfin DSP?...
0 comments posted 20yrs
posted by marco
0 comments posted 20yrs posted by marco