Forcing carry-ripple adder ?

Sylvain, Which synthesis tool are you using? Also, if you could you post a brief example of your code it might help you get an answer. Cheers, Syms.

It does this because it is faster than the carry chain. The carry chain incurs a relatively large propagation time penalty for getting on/off the chain. For anything less than about 7 bits (varies by tool and version of the tool), an adder is inferred without the carry chain. I'm not aware of any way to force it other than instantiation.

I use ISE7.1 last service pack. It's for a SRL based FIFO and I need it to be small. Currently, it can run at 400 MHz (post P&R) but I don't need it that fast but if I could win a few slice ...

Here is the code :

srl_addr_move

"Sylvain Munaut " wrote in message news: snipped-for-privacy@z14g2000cwz.googlegroups.com...

Sylvain, I'm confused. For a FIFO the read and the write counters only need increase. Are you implementing a stack or LIFO? I do concur with Ray. The implementation your synthesis tool has chosen is probably the fastest solution for the reasons he's outlined. Cheers, Syms.

Well, a changing the signals to 8 bits makes what I want and it still works at >360 Mhz wich is good for me ...

I guess, I will instanciate it

It's a synchronous FIFO based on the SRL16 based element and has only a depth of 16.

So I have only 1 counter that tells where to read inside the SRL16. When I write a new data, it's inputed into the SRL16, so that I need to increment the address I read to stay on the same data. When I read a data, I must decrease the pointer to read the next data (time-wise). And if I read and write at the same time, the counter must not move.

SRL16 /--- Data input __V__ |____| |____|

just one question (not directly related to the topic)... if i write A= C+ D in the verilog and choose optimize for speed will the tool generate the CLA adder ???

Try it and see. Synthesis only guarantees to match a netlist to your code.

-- Mike Treseler