Hello,
When implementing a 4 bits up/down counter on a Xilinx FPGA, the synthesis tool doesn't do it the "classic" way, it doesn't use the dedicated carry logic and instead use more LUTs to implement a 5 input - 4 output combinatorial logic and is not especially clever about it since it uses like 8 LUTs to do it ...
All I want is a plain old carry-ripple adder in 4 LUTs ... And if possible I'd like to avoid having to instanciate everything by hand ...
Thanks,
Sylvain