Is it possible to drive global clock routing networks with an internal signal on a Virtex-E FPGA?
I am trying to develop data/strobe enoding on an Virtex-E FGPA. It is required that data and strobe signals are XORed to obtain a clock signal. Then this clock signal will be fed to other logic in the FPGA. Therefore I need to use the XORed signal to use as a clock signal.
Thanks for your replies.
Virtex-E is similar to other Xilinx devices and has internal global clock buffers (BUFG) that can be driven by logic such as an XOR gate as well as an external pin. In fact routing to the global buffer is not even restriced to the global clock input pins, but for external clock sources the input delay is significantly less on these global pins.
If your signals to be XOR'd are external, you don't gain this advantage by using the global clock inputs as the routing must first go to a LUT using non-global resources. In this case it is better to use non-global I/O pins to feed your XOR gate.
It is also possible to run logic signals to a DLL in ther Virtex-E parts. You may need to set the XIL_MAP_ALLOW_ANY_DLL_INPUT environment variable for this. Also this only works for free-running clocks that meet the minimum/maximum frequency limits of the DLL. So if your XOR clock doesn't form a constant clock of fixed period you can't take advantage of the DLL.
Good luck, Gabor
But Gabor i did observed problems while connecting the bufgp to an ordinary I/Opad. It is listed in the lib.pdf that the bufg can take input from global clock pins. One more thing i want to as is that isnt it better to use the clock directly clocking the F/F and to use the strobe to control the input of the F/F rather than mixing the strobe and clock and then use the new output to clcok the F/F. thanks
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