Field-Programmable Gate Arrays

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Xilinx HDLParsers:810 or HDLParsers:3329

Just upgraded to Xilinx ISE 8.1i (a bug for my part in 6.3i resulted in route errors) and am now getting syntax errors....
5 comments posted 20yrs
posted by mattdykes
5 comments posted 20yrs posted by mattdykes

8.1i SP2 download problems

I just tried downloading 8.1i SP2, after Xilinx recently 'improved' their download page. I ended up in an endless loop...
3 comments posted 20yrs
posted by brimdavis
3 comments posted 20yrs posted by brimdavis

is there a way to initialize signals to a value

Hello Is there a way to setup a bit to be tri-stated so that it can be on a bus multiplexed with other signals and only...
6 comments posted 20yrs
posted by clement
6 comments posted 20yrs posted by clement

XPower report precision

Hi, I am using the Xilinx Xpower tool to perform Power analysis. The default precision in the reported power values is...
5 comments posted 20yrs
posted by the.gaffar
5 comments posted 20yrs posted by the.gaffar

Which SelectIO for FPGA <-> FPGA buses?

Hi - I'm doing a board with 17 Virtex-II's on it, which has a 32-bit bus connected between all the devices. A master de...
1 comments posted 20yrs
posted by pdr101
1 comments posted 20yrs posted by pdr101

ModelSim Licence problem

I am using xilinx Tool Ver 6.3. And Modelsim 5.8. Due to some reasons I uninstalled modelsim. After I installed it agai...
2 comments posted 20yrs
posted by pradnya.karande
2 comments posted 20yrs posted by pradnya.karande

ModelSim License Problem

I am using xilinx Tool Ver 6.3. And Modelsim 5.8. Due to some reasons I uninstalled modelsim. After I installed it agai...
0 comments posted 20yrs
posted by pradnya.karande
0 comments posted 20yrs posted by pradnya.karande

Block vs. Distributed RAMs

ISE always seems to infer distributed RAM for async. reads. Is it possible to infer distributed RAM with sync read? Is i...
1 comments posted 20yrs
posted by bhatti1127
1 comments posted 20yrs posted by bhatti1127

Dual Port Block RAM Inference

I infer a Dual Port Block RAM with port A as R/W and port B as R only with dual clock, dual address, dual EN and dual D...
0 comments posted 20yrs
posted by yaseenzaidi
0 comments posted 20yrs posted by yaseenzaidi

Entity with Multiple Architectures

Hi All, I was wondering if anyone has declared an entity with multiple architectures using Xilinx ISE. How is this done...
2 comments posted 20yrs
posted by Sudhir.Singh
2 comments posted 20yrs posted by Sudhir.Singh

I2C and posedge sampling

Has anyone altered the I2C core by Xilinx to sample on the posedge rather than negedge. I am interfacing with the micro...
3 comments posted 20yrs
posted by svasus
3 comments posted 20yrs posted by svasus

Problem programming Altera flex 10k100 & EPC2

I have a working prototype board from yesteryear with a Flex 10K100GC503-3 FPGA and an EPC2L120 configuration device on...
2 comments posted 20yrs
posted by jshamlet
2 comments posted 20yrs posted by jshamlet

EDK Simulation

I am simulating an EDK MicroBlaze embedded system using NC-Sim. Whenever I open a waveform window and try to simulate I...
0 comments posted 20yrs
posted by mottoblatto
0 comments posted 20yrs posted by mottoblatto

microblaze with FSL

I have used sysgen to build a model with microblaze, but i don't know th difference between the two functions: microbla...
1 comments posted 20yrs
posted by zhanghaobegin
1 comments posted 20yrs posted by zhanghaobegin