is there a way to initialize signals to a value

sorry the title is not quite what i ended up asking.

matt

Strange! I didn't understand any thing. Perhaps is it because I have influenza (Yesturday I had 40 degrees celcius) and I'm tired. Try to use short sentences. Provide a small piece of code or example plz. I also had another answer to you question when I read the title. But after reading the core of your message I'm lost.

Mehdi

Matt Clement wrote:

Check the data sheet for your part. Some parts will allow for true

For parts that do support it, you will need to add a line like this (for VHDL):

TSTATE_BUS 'Z');

Note, you can still do this even in later families, but the compiler will turn it into a mux - so be careful. If you aren't aware of that behavior, you can be surprised on large designs with low LUT margins.

Note, I have seen some IP cores that use an 'OR'ed bus structure to solve this problem. With an OR type bus, you just drive zeros when not enabled:

arcitecture rtl of sample is

-- To simplify the OR logic, make these the same width. Your compiler/synthesizer should optimize away bits you don't need - while still making the correct connections. Just load the registers you DON'T need with a constant value. signal My_Bus_1_d, My_Bus_1_q : std_logic_vector( BUS_WIDTH_MINUS_1 downto 0 ); signal My_Bus_2_d, My_Bus_2_q : std_logic_vector( BUS_WIDTH_MINUS_1 downto 0 );

-- Don't worry too much about the My_Data_n busses - you can pad the bus when you feed it to My_Bus_n_d; signal My_Data_1 : std_logic_vector( 3 downto 0); signal My_Data_2 : std_logic_vector( 15 downto 0);

begin

-- You need one of these per *readable* register/entity My_Bus_1_d '0'); My_Bus_2_d '0');

-- To keep your combinational logic path to a minimum, register each "My_Bus". This isn't necessary, and does add an additional clock of latency, but if your timing is marginal, this will help.

S_Regs : process( Reset_n, Clock ) begin if( Reset_n = '0' )then My_Bus_1_q '0'); My_Bus_2_q '0'); elsif( rising_edge(Clock) )then My_Bus_1_q

Actually they do have. Spartan2 spartan2E virtex and virtexE they all have BUFT (or TBUFS)

parts without BUFTs: virtex2/pro virtex4 spartan3/3E

Aurash

Hey guys I am actually using a CPLD by Altera Max 7000S. I have an output pin that needs to either be tristated or drive a '1' at all times other than when driving data on the bus. I have used the second option up until now and it has some weird glitches since it is inside a process and until it gets the first clock it doesnt go to '1'. Maybe if there was a way to initialize it to a '1' at power up. I think the best way is to do a tristate, but I have very little resources left.

Matt

in can go in HI-Z and you use an external pull-up (or internal if available) on this pin.

Aurash