Which SelectIO for FPGA <-> FPGA buses?

Hi -

I'm doing a board with 17 Virtex-II's on it, which has a 32-bit bus connected between all the devices. A master device has to be able to read and write the 16 slaves, and (because of board limitations) I'll probably set this up as two separate buses, with 8 slaves on each bus, and both buses connected to the master. The bus is 50MHz, and the timing isn't critical. The two buses will run most of the length of a PCI card.

Any ideas on what bus interface standard I should be using, and what termination? My first idea was LVCMOS, with parallel (RC at far end) termination. I'm wondering if HSTL or SSTL would be better, and how that affects the termination.

Thanks -


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Pete Robinson
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Do you have the DCI references setup and plugged in properly? If so, you should use the LVDCI. LVCMOS is probably your next best bet unless you have reference voltages plugged into the chips, which most board vendors tend to ignore. The SGI box I have runs HSTL_DCI at 200MHz SDR without an issue. I'm able to DDR LVCMOS at 50MHz on lines of two inches or less without an issue. It works better than LVTTL at that speed. Unfortunately, I'm sure your bus is way longer than that. I think you would definitely need some termination. Hopefully you can use the DCI for all the V2 connection termination. It's unlikely your board has chip termination built in.

For Point to Point, (when I cannot use LVDS) I send a clock along with the data (using an FDDRSE with constants on the data) and then an IBUF delay on the incoming clock before sending it to all the IOB register clock inputs. I also send an enable with the data a busy signal back the other way plugged into an almost-busy signal on the receiving fifo. I usually end up with a dual clock domain fifo on each end. If your distance is longer than a few inches, you will likely need to add a DCM to the outgoing clock and adjust the phase. That gets to be a real pain if you have a lot of chips. 66MHz DDR is the hairy edge of too fast for LVCMOS.

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