I'm doing a board with 17 Virtex-II's on it, which has a 32-bit bus connected between all the devices. A master device has to be able to read and write the 16 slaves, and (because of board limitations) I'll probably set this up as two separate buses, with 8 slaves on each bus, and both buses connected to the master. The bus is 50MHz, and the timing isn't critical. The two buses will run most of the length of a PCI card.
Any ideas on what bus interface standard I should be using, and what termination? My first idea was LVCMOS, with parallel (RC at far end) termination. I'm wondering if HSTL or SSTL would be better, and how that affects the termination.