I2C and posedge sampling

Has anyone altered the I2C core by Xilinx to sample on the posedge rather than negedge. I am interfacing with the microcontroller and the negedge is actually very slow around 200ns because of which a counter bitcnt sometimes increments twice and this leads to problems in the exact transfer of data. It would be nice to know if someone has tried to change the sampling from negedge to posedge. As you can infer I havent actually gone through the entire core.

As well I was wondering whether there is any alternative to this problem. I have read most of the threads about schmitt triggers. but then since this is a bidirectional bus it is not possible to use schmitt triggers i think. as well tried the xilinx app note for schmitt triggers which says something about resistors. but having problems inverting the scl line and getting it out through another port.

Thanks

Regards

Reply to
svasus
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What you can do is drive both lines OpenDrain, and feed both lines via schmitt triggers, into two more pins, SDAf and SCLf, and THOSE are the ones read by the Logic. ie separate PINS for DRIVE and Listen

That way, the problems of double clocking on slow edges is avoided. FPGAs are so fast, the relatively slow rise times of busses like i2c can cause problems....

-jg

Reply to
Jim Granville

I haven't seen the core but I was reimplementing an I2C interface recently. The I2C electrical specs have a glitch tolerance spec for data *and* clock which would mean that sampling the data directly with an edge isn't recommended by the spec. If you use a higher-rate clock to sample both the clock and data, implementing a glitch filter is pretty straight forward.

Reply to
John_H

Thanks for your replies. Happened to find a I2C slave code alone. And since the SCL turned out to be a input alone I could easily put the schmitt trigger and it worked very well.

Reply to
svasus

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