Has anyone altered the I2C core by Xilinx to sample on the posedge rather than negedge. I am interfacing with the microcontroller and the negedge is actually very slow around 200ns because of which a counter bitcnt sometimes increments twice and this leads to problems in the exact transfer of data. It would be nice to know if someone has tried to change the sampling from negedge to posedge. As you can infer I havent actually gone through the entire core.
As well I was wondering whether there is any alternative to this problem. I have read most of the threads about schmitt triggers. but then since this is a bidirectional bus it is not possible to use schmitt triggers i think. as well tried the xilinx app note for schmitt triggers which says something about resistors. but having problems inverting the scl line and getting it out through another port.
Thanks
Regards