Field-Programmable Gate Arrays

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microblaze with FSL

I have used sysgen to build a model with microblaze, but i don't know th difference between the two functions: microbla...

1 20yrs

zhanghaobegin

1 20yrs zhanghaobegin

"does not fanout" warnings with inouts

Hello, I'm working on a project targeting a Lattice Mach4 CPLD using VHDL. In the past I have never used the inout VHDL...

0 20yrs

shawnn

0 20yrs shawnn

Altera RoHS Irony

Today I got this in Altera's email newsletter Get RoHS Compliant with Altera FPGAs, CPLDs and Structured ASICs I have n...

23 20yrs

dsp

23 20yrs dsp

SCHEMATICS ... Is anybody as frustrated as I am with the software?

I've recently noticed that the schematic software that's included with XILINX' ISE WebPack and with Altera's Quartus We...

23 20yrs

richard

23 20yrs richard

Question about using LMB to connect BRAM in MicroBlaze

I am trying to create a MicroBlaze system with 8K instruction memory and 16K data memory. So I use includes a 8K Bram i...

2 20yrs

hy34

2 20yrs hy34

Rocketio, modelsim xe

Hi, I'm trying to implement rocketio on xilinx fpga. Is there a way to simulate it using modelsim XE. I know for the PE...

2 20yrs

info

2 20yrs info

spartan-3e starter kit

I have been waiting to get the spartan 3e starter kit from xilinx for awhile now, but it doesn't seem to be out yet. Do...

13 20yrs

dahl0550

13 20yrs dahl0550

xilinx ise 8.1 mig 1.4 /1.5

hello the ise7.1 had the mig1.4 for memory interface generator does it work on the ise 8.1? if not is there any newer ve...

0 20yrs

MADORIG

0 20yrs MADORIG

ISVLSI 2006 - Call for Participation

+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ + IEEE International Symposium on VLSI 2006 + + +...

0 20yrs

isvlsi06

0 20yrs isvlsi06

[ANN] MicroBlaze uClinux FPGA module (with microwindows) at Embedded

this week Embedded in Nurnberg, Halle 12, Standnummer: 12-338 (TQC): FPGA module with MicroBlaze uClinux on display, no...

2 20yrs

Antti.Lukats

2 20yrs Antti.Lukats

How to decode FAR register in Virtex-4?

Hi everyone, I'm trying to understand how the frame addresses have to be decoded for a Virtex-4 FPGA from Xilinx. So fa...

6 20yrs

bertrand.rousseau

6 20yrs bertrand.rousseau

Newb question about Xilinx Impact and parallel cable III ....

:-) I install new ISE (withh Impact) package from xilinx. Did a simple thing in it and now I,m trying to program my xc9...

4 20yrs

a

4 20yrs a

PacoBlaze updated

Hello folks. I would like to let you know that I have made a new release of PacoBlaze (2.0b). Some bugs noticed by user...

2 20yrs

pablobleyer

2 20yrs pablobleyer

Xilinx + I2C + PPC -> crash

Has anyone seen a PPC crash while using the I2C drivers. I have a simple EDK project with a PPC that reads and writes t...

0 20yrs

matt_news

0 20yrs matt_news

digital logic library by 74xxxx part number?

in the schematic capture of Xilinx ISE, there is ADD symbol button, which will allow you to pick a component by functio...

17 20yrs

aiiadict

17 20yrs aiiadict

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