Entity with Multiple Architectures

Hi All, I was wondering if anyone has declared an entity with multiple architectures using Xilinx ISE. How is this done, whether both architectures are defined in the same file where the entity is declared. Thanks in advance Sudhir

Reply to
Sudhir.Singh
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snipped-for-privacy@email.com schrieb:

Hi Sudhir, what you describe only makes sense for simulation, where you can put in a configuration file, telling the simulator which architecture to use.

In synthesis only one architecture per entity is allowed. You should split your entity and architectures in separate files if still possible.

Another posibility (while not a very clean thing) is to wrap the unused architecture(s) in pragmas:

entity myentity is

-- some ports etc. end entity;

-- synthesis off

architecture unused of myentity is --some crap end architecture unused;

-- synthesis on

architecture which_i_want of myentity is --The real one end architecture which_i_want;

The bad thing is that you always have to edit your sources when trying a different architecture. With separated files you can have separate projects or scripts that use one architecture or the other and have independant reproducable results. So, better spend some time for that than messing around with your sources. Also your CVS (or whatever you use) will be happier.

have a nice synthesis Eilert

Reply to
backhus

backhus schrieb:

I believe immediately that this is the case for ISE and many other VHDL compilers, but it is stupid. Why should a configuration not work for synthesis? I could tell the synthesis tool that I want a wallace tree for multiplier U1 and an array for multiplier U2. This is useful and it also is extremely easy to implement compared to all the other steps that are done in the systhesis process.

I am working in EDA research for many years now and stil can not comprehend why on the algorithm and backend side EDA tools are always pretty close to the cutting edge of technology. But the parser and compiler frontend side lacks at least a decade (more like two decades) behind software compilers. I am baffled when a 80k$ asic targeted vhdl synthesis tool tells me that generics must be of type integer and that I can not have arrays of records and similar bugs.

Kolja Sulimma

Reply to
Kolja Sulimma

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