Xilinx HDLParsers:810 or HDLParsers:3329

Matt; I'm using ISE 6.2.03i, and had similar errors when casting to unsigned, and also to std_logic_vector. That was quite a surprise, since your code looked OK to me. But I'm certainly no expert. I then tried using the "std_match" function, which is in the "numeric_std" library, and that worked. I made output_status a port so that I could verify the logic by looking at the RTL schematic.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all;

entity x is Port ( enable_out : out std_logic; output_status : in std_logic_vector(3 downto 0) ); end x;

architecture Behavioral of x is begin enable_out

Matt; I'm using ISE 6.2.03i, and had similar errors when casting to unsigned, and also to std_logic_vector. That was quite a surprise, since your code looked OK to me. But I'm certainly no expert. I then tried using the "std_match" function, which is in the "numeric_std" library, and that worked. I made output_status a port so that I could verify the logic by looking at the RTL schematic.

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all;

entity x is Port ( enable_out : out std_logic; output_status : in std_logic_vector(3 downto 0) ); end x;

architecture Behavioral of x is begin enable_out

Thanks, Dave. I'm a dumb arse. I'm finishing up a project for a co-worker and didn't notice he was using every library know to man.

Note to self: Don't include ieee.std_logic_signed.all AND ieee.std_logic_unsigned.all.

Guys, Just a FYI, if you Google for "vhdl math tricks of the trade", there's a great article by Jim Lewis all about the wonders of VHDL arithmetic. I use it all the time. The bottom line is to use numeric_std for all new designs. HTH, Syms.

What had me perplexed was that I have a project with lots of glue logic and some simple state machines, and I was doing address compares both concurrently and in a process. I only used the IEEE.std_logic_1164 library. But your original code and my code are basically the same (i.e. adrs = "0010"). But, in my first reply, the only way I could get the test code to compile was to use "numeric_std" and the "std_match" function. So, I'm puzzled - have I overlooked something, or is there a subtle VHDL feature that I haven't learned yet? (gentle responses, please! ;)

-Dave Pollum