Latest threads in Field-Programmable Gate Arrays

Anyone use Xilinx ppc405 profiling tools?

Does anyone use the profiling tools with the Xilinx ppc405? I am trying to profile code on the ppc405 in a Xilinx XC2VP...

9 20yrs

alan

9 20yrs alan

Xilinx document timing diagrams?

I am trying to find some opb_ipif timing diagrams. The Xilinx document "DS404" has figure numbers and titles on the pag...

1 20yrs

mottoblatto

1 20yrs mottoblatto

Xilinx SelectMAP Question

Dear all, I am configuring a Xilinx Spartan 3 using SelectMap (the parallel interface), although the simple details of...

15 20yrs

petermendham

15 20yrs petermendham

Xilinx-XUPV2P- AC97 Audio BSP

Hi all, I'm using XUPV2P xilinx board. In that audio codec chip for AC97 support is avaliable. I plan to use linux-2.4....

0 20yrs

prakash.na

0 20yrs prakash.na

OPB clocking question

Is there information on how to use a user IP that is attached to the OPB with different clock speeds? I currently have...

0 20yrs

mottoblatto

0 20yrs mottoblatto

RFID chip has battary in it or not

Hi, Recently I received a RFID chip to open company's door when entering office building. It is very easy to carry and...

9 20yrs

wtxwtx

9 20yrs wtxwtx

LVDS inputs on Cyclone II

Some time ago I did some experimentation (for a very cost sensitive application) with a Spartan 3 part using an LVDS di...

14 20yrs

nospam

14 20yrs nospam

87C52 & 87C51 core

Does anybody know of an IP vendor that sells the 87C51 & 87C52 IP cores for FPGA's? I have gone through the following I...

6 20yrs

sid.gaddam

6 20yrs sid.gaddam

New To FPGA, Program question

Hello, I am new to FPGAs and was wondering, how do fpga store the bitstream? I mean, with CPLD, I don't need any specia...

5 20yrs

Jim_L_Williams

5 20yrs Jim_L_Williams

how to set a I/O as 3-state in xilinx FPGAï¼Ÿ

hi, there, I want to set one of I/O pin as 3 state, how can I do this in Xilinx FPGA using Verilog? thanks

2 20yrs

paul.pettus

2 20yrs paul.pettus

async. load line on shift register

I just spend days debugging an issue and though I fixed the problem, I don't see why it was an issue in the first place...

3 20yrs

shawnn

3 20yrs shawnn

ChipScope 8.1i. Timing has got worse?

Hi All, I've started using ISE8.1. SP3 has been available awhile, and the angry posts about 8.1 on this newsgroup dropp...

2 20yrs

symon_brewer

2 20yrs symon_brewer

EPLD Lattice Prog Problem

Hi all, I'm developping an application on PowerPC to programm a Lattice EPLD. For that, I'm using ispVM Lattice player....

0 20yrs

max_mont

0 20yrs max_mont

CPU resource type

What kind of cpu resources does fpga "compilation" (Analyse, Synthesis, etc..) use on a cpu..? Integer/Branch/Bitshiftin...

4 20yrs

pbdelete

4 20yrs pbdelete

Cordic-based Sine Computer in MyHDL

Hi: I have added a page about a Cordic-based Sine Computer to the MyHDL CookBook: http://myhdl.jandecaluwe.com/doku.php...

9 20yrs

jan

9 20yrs jan

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