Cordic-based Sine Computer in MyHDL

Hi:

I have added a page about a Cordic-based Sine Computer to the MyHDL CookBook:

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This page demonstrates several features of the MyHDL to Verilog convertor tool. In particular:

- it shows how the convertor takes care of the tricky issues with negative numbers in Verilog automatically

- it shows how you can use non-synthesizable constructs in MyHDL and still get synthesizable Verilog out of it :-) (Really!)

Regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
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Jan Decaluwe
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Jan Decaluwe schrieb:

I heard a research talk on a GI workshop that talked about using simple XSLT translations to make common unsynthesizable VHDL code synthesizable.

IMHO it is embarrassing that a 2006 compiler cannot synthesize

if rising_edge(clk) and enable='1' then...

Kolja Sulimma

Reply to
Kolja Sulimma

Hi Kolja, Just out of curiosity, which compiler are you talking about? XST? Synplify seems fine, I do get a "Feedback mux created for signal xxxxx" warning, but the output doesn't have this mux. Thanks. Cheers, Syms.

Reply to
Symon

Symon schrieb:

I never used synplify, but it is plausible that it has a more modern view on what should be synthesizable and what should not, as the company was started at a time where people allready complained about such limitations.

I discovered limitations like these in the last couple of years in Synopsys FPGA Compiler as well as Design Compiler, in Magma DAs Blast RTL and in XST.

IMHO the worst limitation was a version ov Blast RTL that restricted generics to be of type integer. My code used to turn on feature with boolean values. No it uses integers...

Kolja Sulimma

Reply to
Kolja Sulimma

Wow. A non-trivial example that works. Beautiful generated code. (Ignore the synthesis warnings, I think Jan has it right.) You may be on to something.

Here's how Quartus sees it:

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_______________________ Top-level Entity Name : SineComputer Family : Stratix II Device : EP2S15F484C3 Timing Models : Final Total ALUTs : 276 / 12,480 ( 2 % ) Total registers : 107 [vs. 131 in the example -- apples to oranges ] Actual Time : 141.42 MHz ( period = 7.071 ns ) [ vs 87.385MHz in the example -- apples to oranges ]

-- Mike Treseler

Reply to
Mike Treseler

I don't know of a recent release that causes such embarrassment. The example below works fine on Quartus. The downside to this template is that it clock enables everything in the process -- too restrictive for me.

-- Mike Treseler

___________________________ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity clk_en is generic (vec_len : positive := 8); port ( clk : in std_ulogic; reset : in std_ulogic; enable : in std_ulogic; q : out std_logic_vector(vec_len-1 downto 0) ); end entity clk_en;

architecture synth of clk_en is begin clk_en : process(reset, clk) is subtype vec_t is unsigned(vec_len-1 downto 0); constant vec_init : vec_t := "10110011"; variable reg_v : vec_t; begin -- process template if reset = '1' then init_regs : reg_v := vec_init; elsif rising_edge(clk) and enable = '1' then --< update_regs : reg_v := rotate_left(reg_v, 1); end if; update_ports : q

Reply to
Mike Treseler

Hi Mike, I try to make sure every process (and, of course, every entity) has an enable. Even if the enable is set to '1' in the code, it makes it a lot easier to reuse in future designs with faster clocks. Sadly, I don't always remember to do this. :-( Cheers, Syms. p.s. Jan, sorry for wandering off topic!

Reply to
Symon

Does Quartus issue warnings also?

No doubt the warnings are related to the use of blocking assignments in a clocked always block. You know :-)

At least XST doesn't declare this an error. My worst nightmare would be that half-baked synthesis tools or Verilog gurus would prevent me from writing code like this. It's a realistic possibility that explains my occasional angry outbursts.

What I think happens is that XST creates a FF for any reg in the code. When it detects that the Q output is not used, it issues a warning. Fine with me, as long as it uses the D input wire properly :-)

An interesting side effect is that no warnings are issued in the more "advanced" case when a reg is potentially used immediately but also stored for later usage, like the 'counting' flag in this example:

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Best regards,

Jan

--
Jan Decaluwe - Resources bvba - http://www.jandecaluwe.com
Losbergenlaan 16, B-3010 Leuven, Belgium
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Reply to
Jan Decaluwe

Yes, and the warning isn't even apropos in this case since you've gone belt-and-suspenders with a single named block and local declarations for every reg appearing left of an '='. I will check if I there is some way to stifle the warning.

I knew XST had to be better at something :)

The tools have always allowed it, and I suspect that a silent majority of serious designers have used the style without making a big deal of it. There will always be quiet producers and noisy lint-pickers.

Synthesis really has to do this anyway because wasting flops is a mortal sin.

Yes, synthesis is very clever. Every variable-reg update gets its own little "instance" of gates.

Keep up the good work and don't let the b^st^rds get you down. If I have to learn a new trick, I think I would prefer python to systemverilog.

-- Mike Treseler

Reply to
Mike Treseler

you can add also:

CORDIC Bibliography Site :

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Reply to
vladimir

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