Field-Programmable Gate Arrays

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Phase alignment of DCMs on different boards/devices

Hi group, Scenario: Multiple identical boards with a Virtex-II each all being fed the same clock signal which is being...
4 comments posted 20yrs
posted by doomeddave
4 comments posted 20yrs posted by doomeddave

Voltage Regulator on the XSA-50 board

Hi, Does anyone have the circuit diagram for the voltage regulator on-board the XSA-50 board (manufactured by XESS )? If...
0 comments posted 20yrs
posted by ankur101
0 comments posted 20yrs posted by ankur101

Xilinx 3s8000?

Glory and riches are showered upon those who successfully factor one of the RSA Challenge Numbers (see note [1]) ;-). I...
94 comments posted 20yrs
posted by News5
94 comments posted 20yrs posted by News5

Interfacing Spartan 3 board to PC parallel port??

Hello, I have been working on a project and the submission date is due very soon. Now I am having some problems which n...
11 comments posted 20yrs
posted by kulkarni.shailesh
11 comments posted 20yrs posted by kulkarni.shailesh

How to create a fixed netlist IP core?

I want to learn how to create my own fixed netlist ip cores in Xilinx ISE 8.1 using segments of my existing vhdl source...
0 comments posted 20yrs
posted by colinhankins
0 comments posted 20yrs posted by colinhankins

xst segmentation fault

After making some changes to some hardware that used to synthesize, xst now seg faults. This is using the Xilinx EDK fl...
3 comments posted 20yrs
posted by notreally
3 comments posted 20yrs posted by notreally

ports of multidimentional arrays in verilog.

hi, using verilog how to write a module which has an inpput port for an array of 8 bit signals and how to write a test b...
2 comments posted 20yrs
posted by manusha
2 comments posted 20yrs posted by manusha

Measuring Light with LED and FPGA

Hi Folks, got interested to test it out, and well I have VERY preliminary results - all the test setup was done within...
8 comments posted 20yrs
posted by Antti.Lukats
8 comments posted 20yrs posted by Antti.Lukats

ML405 board

hi Xilinx, do you thing i have a chance to buy an ML405 board before i retire ? i saw the first announcement for this bo...
4 comments posted 20yrs
posted by christophe.alexandre
4 comments posted 20yrs posted by christophe.alexandre

Unreactive Output Pins on Xilinx Virtex-II

Hi, I have some trouble with the outputs of a Xilinx Virtex-II 1000 FPGA. The pins in question are conencted to a bi-di...
9 comments posted 20yrs
posted by Robin.Emery
9 comments posted 20yrs posted by Robin.Emery

ISE8.1 inout, tristate Problem?Please help!

Hi, I use ISE8.1 (webpack) in Verilog. I try to use inout port. Sample code: module ....(... inout wire[7:0] data, ...)...
5 comments posted 20yrs
posted by samxx
5 comments posted 20yrs posted by samxx

Virtex 4 LX25

Hi, does anybody have a list of the unbonded iob's on the lx25? Thanks, Alastair
6 comments posted 20yrs
posted by alastairlynch
6 comments posted 20yrs posted by alastairlynch

How to open an ISE 8.1 project in ISE 7.1?

I want to open an ISE 8.1 project in ISE 7.1, but it seems impossible. and there's even no compatibility property in the...
6 comments posted 20yrs
posted by sutongqi
6 comments posted 20yrs posted by sutongqi

Table-lookup CORDIC

Table-lookup implementation of CORDIC The idea of unification of CORDIC and table-lookup is the follo- wing: taking lef...
0 comments posted 20yrs
posted by vladimir
0 comments posted 20yrs posted by vladimir