Hi All, I've started using ISE8.1. SP3 has been available awhile, and the angry posts about 8.1 on this newsgroup dropped enough for me to upgrade. Anyway, my new angry post is this. I think the new version of Chipscope,
8.1.03i seems to have worse timing than previous versions. When I have a wide capture buffer, say 80 ish, the thing won't place and route at 150MHz. This used to work fine. Also, all my own designs that were close to the timing limit before upgrading have similar if not identical timing, so it's not due to a timing file upgrade.
I wonder if some bright spark in the Chipscope project has reduced the amount of pipelining to save on the amount of real estate? If so, they've buggered the performance when the thing has a wide capture bus.
Anyone else had similar experiences?
Cheers, Syms
p.s. I'm using V2PRO parts.