Some time ago I did some experimentation (for a very cost sensitive application) with a Spartan 3 part using an LVDS differential input as a voltage comparator for a crude delta sigma ADC.
The I/O bank Vcco was 3.3v the common mode on the LVDS inputs was half the
3.3v supply and the differential input voltage was (obviously) limited to whatever it took drive the LVDS input one way or the other.It worked fine.
Now the customer says he wants to use Cyclone II.
I want to run the I/O bank on 3.3v and for Cyclone II I don't want to have to provide a 2.5v supply just for this one input.
So I ask an Altera FAE can I run an LVDS (as a crude voltage comparator) input on 3.3v biased at 1.65v.
After an age I get the answer no, but I could use an LVPECL standard . Even from the very skimpy Altera data I can tell that 1.65v is outside the LVPECL standard common mode range and LVPECL is only available on dedicated clock input pins anyway.
So I ask the question again and after another age get told no, LVDS has to run on 2.5v and no more than 650mV differential input with no further explanation.
I just read through the Cyclone II Device Handbook again and find it says
"Cyclone II devices have one set of VCC pins (VCCINT) that power the internal device logic array and input buffers that use the LVPECL, LVDS, HSTL, or SSTL I/O standards."
So if I believe this the Vccio supply is irrelevant for LVDS receivers and the FAE was talking crap again.
Can anyone confirm this and has anyone experience of using LVDS inputs as voltage comparators on Cyclone II (or Spartan 3/3e for that matter).
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