hi, there,
I want to set one of I/O pin as 3 state, how can I do this in Xilinx FPGA using Verilog?
thanks
how to set a I/O as 3-state in xilinx FPGA？
May 04, 2006
2 Replies
You may want to ask in comp.lang.verilog.
VHDL code:
-- this makes the output "out_pin" hi-impedance when "Z_enable" is a '1'.
-- Otherwise, "out_pin" is assigned the value of "some_bit". out_pin
Moreover, you may need to constrain that pin as a tristate driver by explicitly specifying that to your synthesis tool outside of VHDL.
Regards,
Alif.
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