I recently finished my Masters Thesis on Algorithm Acceleration in FPGA. Part of my research and experiementation was running some algorithms on the PPC405 core in V2PRO. I used both ISE/EDK 7.1 and EDK 8.1 (and then developing IP in the FPGA and attaching to PLB). I got software profiling to work using PIT and I used PLM BRAM memory for storing the profiling information. Initially I ran into a lot of problems, but eventually got it to work on 7.1. I was using latest ISE SP and EDK SP for 7.1. Most of my research was infact done on ISE/EDK
7.1, and towards the end I repeated same experiements using EDK 8.1. Profiling worked on EDK 8.1 also for PPC406 using -pg gcc and setting PIT for software profiling in software platform settings.
Another benchmark I used was a OPB timer that was reset and measured before and after the algorithm started and stopped.
Something noteworthy (and probably makes a lot of sense) is the EDK8.1 generated a lot faster software (EDK 7.1 and 8.1 was compared for -O0,
-O1, -O2, -O3) on the -O2 and -O3 gcc options, but this is probably most likely do to the fact they are using a newer version of GCC in EDK
8.1. Alan, If you have any specific questions you can email me, and I can tell you my experiences using sw profiling in 7.1. It was quite a hassle but eventually worked.