Field-Programmable Gate Arrays

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Fast Serial I/O on Virtex-5

http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/index.htm Looking at Virtex-5 capabi...
5 comments posted 20yrs
posted by already5chosen
5 comments posted 20yrs posted by already5chosen

JTAG in-system programming of PROM devices

Hi, I've a question regarding in-system programming of prom devices using the JTAG (ieee 1532) protocol. I implemented...
1 comments posted 20yrs
posted by r-m-w
1 comments posted 20yrs posted by r-m-w

PCI related doubts !!!!!!

Could somebody explain the use of lines AD[1:0] during address phase, for transfers to the I/O space.
0 comments posted 20yrs
posted by jpvarkey
0 comments posted 20yrs posted by jpvarkey

XC9572 Readback

Hi! I am facing a problem regarding Xilinx CPLD Readback. One of our engineers left the country who designed the system...
1 comments posted 20yrs
posted by shabana_rizvi
1 comments posted 20yrs posted by shabana_rizvi

PCI related documents

I would like to know more about configuring PCI.Could you suggest some documents which would help me.I would like to kn...
1 comments posted 20yrs
posted by jpvarkey
1 comments posted 20yrs posted by jpvarkey

ISE 8.1 with 7.1

Hi, I'm currently working with ISE 7.1 SP4, but I'd now like to try the 8.1 SP3 version. Can I install 8.1 on the same...
7 comments posted 20yrs
posted by marco
7 comments posted 20yrs posted by marco

Specifying a non connected port

Is there a way, when instantiating a module in Verlog, to specify that a certain output port of the module was intentio...
0 comments posted 20yrs
posted by cairosearch
0 comments posted 20yrs posted by cairosearch

fpga uclinux, good starter board ?

hi folks, i'm looking for suggestions on a good starter board/fpga so i can try my hand at getting uclinux to run on an...
8 comments posted 20yrs
posted by webnews1
8 comments posted 20yrs posted by webnews1

COREGEN: DCM

When I used coregen to create a DCM it provided the simulation code in verilog (ISE 8.1). My old projects in 7.x create...
1 comments posted 20yrs
posted by weddick
1 comments posted 20yrs posted by weddick

Peripheral connected to multiple OPB buses

Hi, I was wondering if it is possible to design a peripheral (for Microblaze) in EDK 7.1 which is connected to more than...
7 comments posted 20yrs
posted by vidyutg
7 comments posted 20yrs posted by vidyutg

DVI connected to Virtex-4

Hallo, I have read about the chipsync technology based on iserdes implemented on Virtex-4. May I use it to connect a DV...
0 comments posted 20yrs
posted by marc
0 comments posted 20yrs posted by marc

tft and uClinux

Hello everyone, I am in process of designing my own Spartan-3 board capable of running uClinux. On board, I have SDRAM,...
9 comments posted 20yrs
posted by orpid.yu
9 comments posted 20yrs posted by orpid.yu

Xilinx EDK library size issue

I moved an EDK project I have from V8.1i back to V7.1i When I compiled my software, the elf was twice the size and over...
0 comments posted 20yrs
posted by sgfallows
0 comments posted 20yrs posted by sgfallows