Latest threads in Field-Programmable Gate Arrays

How to add a peripheral IP generated by Coregen to EDK?

Hi, I'm trying to add an IP(FFT), generated by Coregen, to an EDK project. I have created a new custom IP in EDK and ad...

1 20yrs

minjun.zhao

1 20yrs minjun.zhao

Fast Serial I/O on Virtex-5

http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/capabilities/index.htm Looking at Virtex-5 capabi...

5 20yrs

already5chosen

5 20yrs already5chosen

JTAG in-system programming of PROM devices

Hi, I've a question regarding in-system programming of prom devices using the JTAG (ieee 1532) protocol. I implemented...

1 20yrs

r-m-w

1 20yrs r-m-w

PCI related doubts !!!!!!

Could somebody explain the use of lines AD[1:0] during address phase, for transfers to the I/O space.

0 20yrs

jpvarkey

0 20yrs jpvarkey

ngdbuild:604 - storing netlists in other directories than the project dir

Hi All, Has someone figured out how (or if) it is possible to store netlists used in an ISE design in other directories...

3 20yrs

xjohbex

3 20yrs xjohbex

XC9572 Readback

Hi! I am facing a problem regarding Xilinx CPLD Readback. One of our engineers left the country who designed the system...

1 20yrs

shabana_rizvi

1 20yrs shabana_rizvi

PCI related documents

I would like to know more about configuring PCI.Could you suggest some documents which would help me.I would like to kn...

1 20yrs

jpvarkey

1 20yrs jpvarkey

ISE 8.1 with 7.1

Hi, I'm currently working with ISE 7.1 SP4, but I'd now like to try the 8.1 SP3 version. Can I install 8.1 on the same...

7 20yrs

marco

7 20yrs marco

Specifying a non connected port

Is there a way, when instantiating a module in Verlog, to specify that a certain output port of the module was intentio...

0 20yrs

cairosearch

0 20yrs cairosearch

fpga uclinux, good starter board ?

hi folks, i'm looking for suggestions on a good starter board/fpga so i can try my hand at getting uclinux to run on an...

8 20yrs

webnews1

8 20yrs webnews1

COREGEN: DCM

When I used coregen to create a DCM it provided the simulation code in verilog (ISE 8.1). My old projects in 7.x create...

1 20yrs

weddick

1 20yrs weddick

Peripheral connected to multiple OPB buses

Hi, I was wondering if it is possible to design a peripheral (for Microblaze) in EDK 7.1 which is connected to more than...

7 20yrs

vidyutg

7 20yrs vidyutg

DVI connected to Virtex-4

Hallo, I have read about the chipsync technology based on iserdes implemented on Virtex-4. May I use it to connect a DV...

0 20yrs

marc

0 20yrs marc

Potential of the CELL Processor for Scientific Computing

This was just posted in c.a.e, but could have potential for fast simulation times in FPGA developments ? :) I presume t...

1 20yrs

no.spam

1 20yrs no.spam

tft and uClinux

Hello everyone, I am in process of designing my own Spartan-3 board capable of running uClinux. On board, I have SDRAM,...

9 20yrs

orpid.yu

9 20yrs orpid.yu

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