Field-Programmable Gate Arrays

initial block processing in XST 8.1, part 2

All- On pg 498 of the 8.1i XST Users Guide, it says "Since initial blocks are ignored during synthesis...". But our FAE...

0 comments posted 20yrs

posted by jbrower

0 comments posted 20yrs posted by jbrower

Xilinx IP wizard help

I have a design from ISE that I have been trying to create a peripheral out of. I have created peripherals before using...

4 comments posted 20yrs

posted by joeylrios

4 comments posted 20yrs posted by joeylrios

DCM lock - require clarification

Hi, I am using the VirtexII DCM in my design to generate the master clock for all the modules in my design. The input f...

1 comments posted 20yrs

posted by g.shrinivasan

1 comments posted 20yrs posted by g.shrinivasan

Agility - user experiences? (newbie)

Hi, Has anyone got experience using Celoxica Agility to synthesise SystemC? I haven't had much luck using version 1.0 (...

0 comments posted 20yrs

posted by goldenorfe

0 comments posted 20yrs posted by goldenorfe

ADV7321 interlaced mode

Hello, I'm trying to set PAL on adv7321, but the output signal is progressive timing mode. Does anybody know what is pro...

2 comments posted 20yrs

posted by mstep

2 comments posted 20yrs posted by mstep

FPGA : FFT

Hi I wanted to implement FFT in FPGA. I would like to do it using the CORDIC technique. Can anyone help to understand th...

1 comments posted 20yrs

posted by pbijoy

1 comments posted 20yrs posted by pbijoy

Altium Livedesign eval boards - can you add a configuration prom?

I've been eyeing the Altium Livedesigner evaluation boards as a potentially cheap way to get a reasonably powerful FPGA...

3 comments posted 20yrs

posted by jshamlet

3 comments posted 20yrs posted by jshamlet

Synthesizing VHDL delays [noob]

Hi! I have a question regarding the VHDL's "after" keyword. I've read that it is not synthesizable but only used for si...

2 comments posted 20yrs

posted by nema

2 comments posted 20yrs posted by nema

DSP48E, What are the internal implementations used?

Hello PPL, I would like to know what are the current implementations for the internal blocks inside a DSP48E. This of c...

10 comments posted 20yrs

posted by jaxato

10 comments posted 20yrs posted by jaxato

Startup in Dynamic Reconfigurable Computing needs a FPGA Designer

Be part of the first wave of hires to join this exciting new startup to become the leading provider of programmable cop...

0 comments posted 20yrs

posted by walterwwongjr

0 comments posted 20yrs posted by walterwwongjr

Xilinx ML321 (v2pro rocket io): Adding PCIe functionality

Hello All, We are looking into the Xilinx PCI Express Endpoint Logicore to develop a high speed serial link on the Xili...

2 comments posted 20yrs

posted by ok

2 comments posted 20yrs posted by ok

using Altium DXP2004 with Virtex4, also soft processors

even though DXP2004 doesnt support S3-V4 architectures (that suppor it only in Altium Designer 6) it still possible to...

0 comments posted 20yrs

posted by Antti.Lukats

0 comments posted 20yrs posted by Antti.Lukats

ISE .ant file

Hi, what is this .ant file? I'm working with ISE 7.1, I added a test bench waveform to my project and then I choose "Ge...

0 comments posted 20yrs

posted by marco

0 comments posted 20yrs posted by marco

Metastability question (newbie)

Hello, Please excuse me posting a presumably lame question here, but despite a rather thorough search I can't find answ...

2 comments posted 20yrs

posted by tomdz

2 comments posted 20yrs posted by tomdz

ChipScope and the FPGA Editor ILA command

Hi, I've been experimenting using the FPGA Editor to modify ChipScope monitor/trigger signals and reduce the requiremen...

1 comments posted 20yrs

posted by vivian.bessler.nospam

1 comments posted 20yrs posted by vivian.bessler.nospam