When I used coregen to create a DCM it provided the simulation code in verilog (ISE 8.1). My old projects in 7.x created these in VHDL. Is there a way to select which code type is created? I do everything in VHDL.
Thanks, Joel
COREGEN: DCM
May 28, 2006
1 Replies
Hi Joel, Goto Project->Project Options->Generation in Coregen. There is a "Design Entry" option in which you can choose between Verilog and VHDL code generation.
Regards, Srini.
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