tft and uClinux

What TFT screen model do you use ..? Voltage level it requires ..? Data format ..?

Thanks for your interest,

I still didn't decide strictly what type of display, but it is going to be something like this module...

or this

I think this is standard connection for module like this, isn't it?

So question is... how to connect this type of display to SPARTAN-3 and control it from uClinux?

I realize that it have to be some core connected to PLB (?) or some other BUS on one side, and to I/O pins on other side in microblaze configuration? Am I right?

Thank you for your efforts to help me

Branko Karaklajic

Look at the CPUs that have LCD video interface. For example PXA255 from Intel. Plenty of docs at their web site. That will give you some idea.

In general the (soft in your case) CPU should just write to a frame buffer. And some logic in the rest of the FPGA should scan that frame buffer and send bits to the LCD lines. For most panels there are 8 or 16 data lines and 3 clocks - pixel, horizontal and vertical.

-Alex.

what I did was to modify xilinx ip core to work with the display

the issue was that PLB is not supported in S-3 by default so you need to change several IP cores in EDK to enable s-3 family support

as og linux support the microwindows application was compiled to directly work with the tft ip core, I did not have linux framebuffer driver at all. I tried by the framebuffer required several other drivers and some of them did not want to compile

but xilinx framebuffer linux driver should be easy starting point

anyway beware of the memory bandwidth, with single bank

Antti

A quick read of the datasheet. I think it goes something like this. Set VSHD to the same voltage as the spartan (3.3) select LVTTL output. As this seems to be the way to determine the V-IL and V-IH.

Define a buffer of N1 bits that will satisfy this equation: N1 = ceil(display_bits/memory_bits)

In the case of 18 bit display and 8 bit memory, N1 becomes =3.

Then read a "word" of memory externally and put it in a buffer of the size N1. Do this until buffer is full. Then await clocking of data to display before letting the "memory counter" on loose again. It will need at most ceil(display_bits/memory_bits) cycles of transfer for every pixel.

Drive VCOM and CS. Then setup a master clock at N1 x pixelclock. In this case pixelclock=DCLK. Use master clock + counter output to drive N2 bits. In this case N2 ought to be in the ballpark ceil(ln(320*240)/ln(2)) = 17 bits. So a 16-bit counter should do it.

Then you drive AND gates, with inputs inverted as to make it active at a predetermined value of the counter output. And latch the output of the AND-gate for use on the opposite flank of the one that triggers the counter.

Make certain counter values trigger LP, SPL, CLS, PS, SPS, memory fetch to appriate level.

This should get you started..

Don't forgett those analogue signals aswell .. ;) (for contrast/brightness)

There's also some lcd driver at opencores.org iirc.

Well, I just succeeded to do similar thing. Can you, please, tell me how much of FPGA is used after your design was completed.

a system with:

microblaze opb_ethernet opb_uart opb_gpio opb_spi opb_sdram plb_sdram plb_display (the xilinx modified)

Dear Antti, I am new with EDK environment and want to interface with SDRAM, but when i add device SDRAM into my project my tool Xilinx EDK 7.1 doesn't include driver for SDRAM and also not including any API file for that, so please suggest some remedy for the same if possible

there is no driver needed just access the memory with volatile pointer thats it

antti