Field-Programmable Gate Arrays

Interface of 8051 microcontroller with FPGA Block RAM

Hi, Can I use Block RAM for data storage in a system involving micro-controller which writes into Block RAM as a buffer...

7 comments posted 19yrs

posted by makarand.deshmukh

7 comments posted 19yrs posted by makarand.deshmukh

XPLA3 and Spartan3 Devices Do Not Respond to Programming via Parallel 3 Cable

I have a 4 layer, development board in prototype stage. The board has an XCR3128XL CPLD and a Spartan 3 XC3S400 FPGA bo...

0 comments posted 19yrs

posted by bkhicks2001

0 comments posted 19yrs posted by bkhicks2001

spartan 3e starter kit usb cable

Hi all, Recently I bought a Spartan 3E starter kit board and met some configuration problems. As indicated in the user...

4 comments posted 19yrs

posted by eejju

4 comments posted 19yrs posted by eejju

V2PRO30 Check

Group, Can somebody check my understanding on the V2PRO30? I currently have some LVTTL single ended signals that are cu...

2 comments posted 19yrs

posted by robnstef

2 comments posted 19yrs posted by robnstef

Open-source CableServer for Impact (no more need for Jungo driver on Linux)

I've reversed engineer the CableServer communication with Impact and written from scratch a brand new CableServer. Curr...

8 comments posted 19yrs

posted by zcsizmadia

8 comments posted 19yrs posted by zcsizmadia

How to active a disappeared HDL source file in the project of ISE webpack

Hi, I am new to Xilinx ISE webpack 8.2. Occationally, I selected "none" selection among (simulation, synthesis/implemen...

2 comments posted 19yrs

posted by rxjwg98

2 comments posted 19yrs posted by rxjwg98

PCI/PCI-X IDSEL

Hi i am designing a PCI-X 64-bit 66 Mhz Device in FPGA, connected with a SBC (without backplane), the Spec says that ID...

3 comments posted 19yrs

posted by yy7d6

3 comments posted 19yrs posted by yy7d6

easics - crc equations

Does anyone know what happened to the easics.com site ? I wanted to use their CRC equation generator. This was working...

2 comments posted 19yrs

posted by brucenutbrown

2 comments posted 19yrs posted by brucenutbrown

MPMC2 : npi issues

Hi, I am exploring the possibility to use the npi(native port interface) towards the MPMC2(multi port memory controller...

2 comments posted 19yrs

posted by ivo

2 comments posted 19yrs posted by ivo

FFT IP CORE: XFFTV2.0

Who has once used the fft ip core: xfft v2.0? Can you gave me some advice?

1 comments posted 19yrs

posted by zyl-02042101

1 comments posted 19yrs posted by zyl-02042101

Number of Modules in a Verilog File

Hi, Is there any method to increase number of verilog modules/instances in a single verilog file, While sythesizing wit...

0 comments posted 19yrs

posted by jitendrakumawat

0 comments posted 19yrs posted by jitendrakumawat

Bypass Caps : XAPP623 vs Spartan-3 Starter Kit Board

Hi, I want to design a development board containing Xilinx Spartan-3 XC3S400. My problem is regarding the number and va...

6 comments posted 19yrs

posted by jidan1

6 comments posted 19yrs posted by jidan1

Spartan 3 PCI-X 133Mhz

Hi has anyone have tried to implement a PCI-X 133Mhz core in a Xilinx Spartan 3 FPGA?

1 comments posted 19yrs

posted by yy7d6

1 comments posted 19yrs posted by yy7d6

virtex xcv:no way to see TDO moving:

hi to all the ng for practicing vhdl at home 3 months ago i builded a modified cable 3 and i tried to make my pc commun...

1 comments posted 19yrs

posted by blisca

1 comments posted 19yrs posted by blisca

ISE licensing

Is it possible to revert to a Webpack license once the full 60 day evaluation license has expired on ISE? If so how is...

4 comments posted 19yrs

posted by enquiries

4 comments posted 19yrs posted by enquiries