Field-Programmable Gate Arrays

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ISE licensing

Is it possible to revert to a Webpack license once the full 60 day evaluation license has expired on ISE? If so how is...
4 comments posted 20yrs
posted by enquiries
4 comments posted 20yrs posted by enquiries

pull-ups for Spartan3

Hi, for my Spartan3, being the internal pull-ups only good for non connected pins, which external pull-ups should I pla...
1 comments posted 20yrs
posted by marco
1 comments posted 20yrs posted by marco

xgpio_DiscreteRead

Hi Everybody I have this problem with my Microblaze. No mater what I do I can not read a simple data from GPIO (DIP Swi...
0 comments posted 20yrs
posted by jerzy.zielinski
0 comments posted 20yrs posted by jerzy.zielinski

Performance Appraisals

Hello, I'm posting this question here because I want responses from engineers, so please don't be offended. I want to k...
145 comments posted 20yrs
posted by jjlindula
145 comments posted 20yrs posted by jjlindula

Aurora implementation

Here is my potential setup: 1. N-boxes connected to a single box (Spoke to Hub config) via RocketIO running the simplex...
2 comments posted 20yrs
posted by vt2001cpe
2 comments posted 20yrs posted by vt2001cpe

Xilinx Spartan-3A

What is this device supposed to featured. Start the rumor mill. -Eli
1 comments posted 20yrs
posted by emh203
1 comments posted 20yrs posted by emh203

FPGA support for DDR3 and GDDR3

Does anyone know of a FPGA that supports DDR3 and/or GDDR3 dram protocols? These drams use some new signalling levels an...
0 comments posted 20yrs
posted by johnp3+nospam
0 comments posted 20yrs posted by johnp3+nospam

fx12 v fx20 static power?

Has anyone actually measured the static power of the V4fx12 and v4fx20. I'd like to upgrade my design for the larger ch...
1 comments posted 20yrs
posted by someone
1 comments posted 20yrs posted by someone

Virtex-4FX DCM autoshutdown failure, any suggestions

Hi if anyone has seen the same or has any ideas how to avoid the issue I am faced please help - I am trying to get it s...
13 comments posted 20yrs
posted by Antti.Lukats
13 comments posted 20yrs posted by Antti.Lukats

behavioral vs post-P&R simulation mismatch

I know this topic has been discussed before, but i am looking for some ideas. My design is synchronous, I use ISE8.2.02...
4 comments posted 20yrs
posted by tullio.grassi
4 comments posted 20yrs posted by tullio.grassi

MGT Power supply

Hi I have several questions powering the AVCCAUXRX/TX MGT power supply: -Are switching regulators allowed or should lin...
5 comments posted 20yrs
posted by heinerlitz
5 comments posted 20yrs posted by heinerlitz

power measurement on the board...

Hi guys, I'm trying to measure the power consumption on the board instead of using XPower. From the previous posts I kn...
0 comments posted 20yrs
posted by amirhossein.gholamipour
0 comments posted 20yrs posted by amirhossein.gholamipour

FF1152 Development board....

Hi guys, Currently in my experiments I'm using an FF1152 Development Board originally by Memec. The FPGA chip on the bo...
0 comments posted 20yrs
posted by amirhossein.gholamipour
0 comments posted 20yrs posted by amirhossein.gholamipour

Location of Virtex4 ASCII pinout tables

I go to www.xilinx.com, and click on "Virtex 4 FPGA" (on the left under "Products") This brings up the URL http://www.x...
4 comments posted 20yrs
posted by pmaupin
4 comments posted 20yrs posted by pmaupin