Hi, Is there any method to increase number of verilog modules/instances in a single verilog file, While sythesizing with Xilinx Project navigator?
If there are more than about 50 modules in a single verilog file it is not taken by project navigator, and it shows a '?' ahead of these modules. Like the modules are missing but actually they are not.
If any one have some solution, please put forward.
Thanks n regards, Jiten