Bypass Caps : XAPP623 vs Spartan-3 Starter Kit Board

First, please note that the Spartan-3 starter kit was not designed by Xilinx. Digilentinc.com is where you should find the trail ending. Just because a manufacturer recommends something doesn't mean board developers are going to follow it.

Glancing through XAPP623, it's surprising how many points we've *just* been talking about this last week here on this forum are touched upon. As that discussion went, there's more than one approach to a solution that can work for your needs.

One suggestion I'd give regarding your cap numbers: round up.

The numbers you have may work very well. There's no guarantee that it's the "best" or most appropriate solution for the board you need. In the XAPP623 example, there's no adjustment to capacitor count for plane spacing demonstrating where "all" the information might not be there.

One suggestion: buy a book from a guy named Ritchey. Just search on this group for his name using google or similar search tool and you'll find many posts from this past week. More ideas are presented in those posts.

snipped-for-privacy@hotmail.com wrote:

see

and look at the thread:

"placing addiional caps across existing caps to reduce noise"

...snip...

These general recommendations are just that, general. To know how to bypass a design first requires that you analyze your design to know how much noise you can accept on the power plane and how large the current transitions will be so you can calcualate a target impedance. It is useful if you know how many outputs will be driving at what rate and what length transmission lines. This can be used to get an idea of the current spikes when your outputs change. These can also be analyzed for frequency content.

Then to design your power distribution you should provide capacitance of various values to give the required impedance from about 1 kHz (the high end of where the PSU is effective) to the max frequency determined by your edge rates. I recommend that you use tantalums for the low frequency range and several values of ceramic caps to smooth out the impedance at the mid frequencies. Finally the power plane should be closely spaced to the ground plane to provide good high frequency decoupling. If your design has many fast edge rates you may want to simulate the signals as well as the power decoupling.

When you read an app note and the vendor says they won't guarantee that the part will work if you don't follow the app note, does that mean if you follow the app note they *do* guarantee your design???

hellofa good question :)

Hi JJ, I suspect the truth of the matter is that it's hard to get this wrong. As long as you have enough capacitors with low impedance paths to the device, you're laughing. As to what is enough, one per power pin is a pretty good place to start. Use the biggest value in the smallest package you can. Some folks would apparently have you design power planes for each supply, that's three planes for your design. Kinda defeats the point of using a low-cost FPGA, save a few quid on an FPGA and then burn it on PCBs. You might consider routing the power and making sure you tie the power pins together at the device with a copper pour. Make _sure_ you don't skimp on ground planes. Also, some folks recommend a bunch of different values because of serial self resonant frequencies. In _my_ view this is bollocks, the Q of ceramic caps is so poor the effect is minimal. If the Q were better, you'd get problems with impedance peaks at the parallel resonances. As FPGA toys mentions, we've been thrashing this out in another thread. Why not have a read? It's kept me entertained for a few days! :-) Best wishes, Syms.

I can recommend the high capacity MLCC caps in 1210 size housing. Tantalums are not so reliable and can cause severe damage to the PCB when placed reverse.