Interface of 8051 microcontroller with FPGA Block RAM

Mak schrieb:

yes, you can. I assume you are considering the BRAM to be used memory for an external 8051 MCU? You need to create some clock for the BRAM through and see that the timings are met. For first testing you can just use some onchip oscillator to supply some free running clock over

100Mhz to the BRAMs, so they would become sort of synched pseudo RAMs. The BRAMs would make multiply read and writes each 8051 cycle but should not bather as long as the addr-data are valid for writes, and the 8051 read is slow enough for at least 1 BRAM read to happen always before the 8051 latches read data.

Antti

Thank you Antti, The faster clock from FPGA will decode the WR logic repetatively, which may cause multiple data writes to the BRAM. I could not understand what you meant by "The BRAMs would make multiply read and writes each 8051 cycle, but should not bather as long as the addr-data are valid for writes"

My application involves writing the data block to memory and reading the RAM back using it for transmission.

Antti wrote:

Mak schrieb:

well as long as address and data are valid during all the time the WR is active then the multiply writes of the same data to same address would not matter. Antti

Yep, you can interface Block RAM to an 8051. I have a SiLabs C8051F340 design that does just that -- it uses the block RAM as a display buffer for a simple LCD controller. Actually, the BRAM is implemented as a true dual port, and the sides have different clocks and different port widths. Works fine.

The "micro" side of the memory is clocked by the '340's SYSCLK output at 48 MHz.

-a

Just use the write enable signal as the clock signal and you'll be fine.

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do you have any clock on board?