Hi, I am new to Xilinx ISE webpack 8.2. Occationally, I selected "none" selection among (simulation, synthesis/implementation only, etc.) to a test bench VHDL file. I cannot add the test bench to make a simulation anymore. When I add existing file, it says that file has been added, it is not necceary to add it. How to make it reappear in the source tab?
Thank you very much.
fl,
I believe you'll find your source file in the Libraries tab (probably under the work library), where you should be able to right-click on it and select properties. From there, you can choose the correct association and the source should then be back in the Sources tab.
I hope that helps.
-Kamal
fl wrote:
I found a similar behaviour in the stand alone Xilinx Modelsim. There obviously is a window update problem. But the window has a right mouse function giving you the opportunity to update the window manually. Then the files are visible again.
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