Hi, I am new to Xilinx ISE webpack 8.2. Occationally, I selected "none" selection among (simulation, synthesis/implementation only, etc.) to a test bench VHDL file. I cannot add the test bench to make a simulation anymore. When I add existing file, it says that file has been added, it is not necceary to add it. How to make it reappear in the source tab?
Thank you very much.