Hi i am designing a PCI-X 64-bit 66 Mhz Device in FPGA, connected with a SBC (without backplane), the Spec says that IDSEL for the first slot be routed to AD32, IDSEL for the 2nd slot is AD31 and so on, does this mean that i don't need to have an I/O assigned for IDSEL in my FPGA? and refer to AD32 for IDSEL during configuration transaction?
BTW, i use Xilinx Spartan 3 fpga. Thanks.