Hi i am designing a PCI-X 64-bit 66 Mhz Device in FPGA, connected with a SBC (without backplane), the Spec says that IDSEL for the first slot be routed to AD32, IDSEL for the 2nd slot is AD31 and so on, does this mean that i don't need to have an I/O assigned for IDSEL in my FPGA? and refer to AD32 for IDSEL during configuration transaction?
BTW, i use Xilinx Spartan 3 fpga. Thanks.
I don't believe AD32 is a specific requirement, just a suggestion. If your FPGA is embedded on the PCI bus and not interfaces to a slot that has a slot IDSEL assigned, then yes, you can hard-wire the IDSEL of your PCI core to the selected AD line either inside your device or through a resister external to the device. It won't matter to your embedded system which approach you use.
Ayon kay John_H:
The Single Board Computer (SBC) to which the PCI Device is to connect does not have IDSEL on its Edge fingers, also it has CLKA,CLKB,CLKC, and CLKD to pair with REQ0#-GNT0# to REQ3#-GNT3#. So i will have to either try both.
Typical single board computers with edge fingers expect to plug into a passive backplane that routes the multiple REQ/GNT pairs and clocks to individual slots and gives each slot an associated IDSEL. So you really only need to pick one of the expected configurations, for example REQ0#-GNT0# and IDSEL on AD32. Make sure to pull up unused REQ# signals.
As a side note, I would double check the IDSEL routing recommendations. Normally only bits 16 through 31 are used, where 16 corresponds to slot 0 and 31 to slot 15. I've never seen AD32 or any of the extended 64-bit signals used for IDSEL.
Regards, Gabor
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