Field-Programmable Gate Arrays

Xilinx Floorplanner 'Replace All With Placement' and still logic left over!

Ok, it's been a while (a few versions) since I've had to use the Xilinx Floorplanner. But I don't recall this happening...

1 comments posted 19yrs

posted by hyarbr01

1 comments posted 19yrs posted by hyarbr01

RocketIO, MGT documentation. Does MGT clcok have to be 50% duty cycle?

Is it just me or is the documentation for the RocketIO (MGT) for the Xilinx Virtex4 very bad? I'm trying to find duty c...

2 comments posted 19yrs

posted by dale.prather

2 comments posted 19yrs posted by dale.prather

Xilinx Synchronous FIFOs

Hello, I have been looking at my FIFO designs and considering if they are backward compatible from Virtex4 to Spartan....

1 comments posted 19yrs

posted by bradsmallridge

1 comments posted 19yrs posted by bradsmallridge

picoblaze RS-232 using 62.5 MHz

Hi, I was currently using picoblaze with RS-232 with the FPGA running at 50 MHz and it worked fine. I now need to run i...

5 comments posted 19yrs

posted by axr0284

5 comments posted 19yrs posted by axr0284

Quick question on Coolrunner II IO voltages

Hi chaps I'm fairly sure I can power down the IO buffers of a Coolrunner II with the internal logic powered, but I'm lo...

1 comments posted 19yrs

posted by PeterSmith1954

1 comments posted 19yrs posted by PeterSmith1954

EDIF generation from C

Hello As I'd mentioned in one of my previous mails, I'm working on intrinsic evolution. I'd like to know if its possibl...

4 comments posted 19yrs

posted by fyp.quadruples

4 comments posted 19yrs posted by fyp.quadruples

altera MAX II dev kit LCD mountings??

hi will a simple undolder and remounting at 90 degrees give an angled display or is super glue holding the thing in pla...

0 comments posted 19yrs

posted by jackokring

0 comments posted 19yrs posted by jackokring

Santa Clara Connector and LVTTL etc

hi looks like the 40 pin connector on the max II development kit is IDE ATA pin compatable, but is LVTTL or LVCMOS sign...

0 comments posted 19yrs

posted by jackokring

0 comments posted 19yrs posted by jackokring

Transport Delays in Modelsim

Has anyone ever been able to get Modelsim to model transport delays in Verilog? Verilog simulators, by default, use ine...

6 comments posted 19yrs

posted by kevin_neilson

6 comments posted 19yrs posted by kevin_neilson

inserting text into a video stream (from a pre-existing video source)

I would like to superimpose some text into a video stream coming from a camera into my fpga. Lets say I would like to p...

8 comments posted 19yrs

posted by wallge

8 comments posted 19yrs posted by wallge

Can I use 3.3V clock into the MGTCLK? MGT RocketIO

I have a 3.3V (differential, LVPECL) clock for my MGTCLK. Are they 3.3V tolerant? Is there anyway of making this work wi...

4 comments posted 19yrs

posted by dale.prather

4 comments posted 19yrs posted by dale.prather

LWIP EXAMPLE??

Has anybody any LWIP example?. I try to connect PC and Board. I try to send some package with tcp_write but I have erro...

3 comments posted 19yrs

posted by pbantunez

3 comments posted 19yrs posted by pbantunez

Is this Multi-Cycle Path ?

Hi all, I have a design which has 15 blocks. Data enters from 1st block and after 60 clocks comes out from 15th block....

1 comments posted 19yrs

posted by vedpsingh

1 comments posted 19yrs posted by vedpsingh

VHDL Model of a stepper motor

Anybody allready designed a VHDL model of a stepper motor to simulate in modelsim ?

3 comments posted 19yrs

posted by fpgaengineerfrankfurt

3 comments posted 19yrs posted by fpgaengineerfrankfurt

P160 analog module ?

Hi, I just buy a P160 analog module from Memec Design and I'd like to know the type of the 7 analog connectors. Because...

1 comments posted 19yrs

posted by matthieu.cattin

1 comments posted 19yrs posted by matthieu.cattin