1. Home
  2. Field-Programmable Gate Arrays
  3. Xilinx Floorplanner 'Replace All With Placement' and still logic left over!

Xilinx Floorplanner 'Replace All With Placement' and still logic left over!

Ok, it's been a while (a few versions) since I've had to use the Xilinx Floorplanner. But I don't recall this happening before. Virtex 5, after place and route I'm in the FPGA Editor and I switch the filter to 'Unplaced Components.' None there! I load the same design in Floorplanner and execute 'Replace All with Placement.' Some symbols do get placed, but not all of them. I'm seeing some symbols including FG's left over in the Design Hierarchy window. What gives??? Is there an optimization step between .ngd/.ncd and final place/route where these rogues are taken out?

- Craig

Reply to
Craig Yarbrough
Loading thread data ...

Take a look at the unplaced components ... I'm guessing they are all route-throughs (will have _rt at the end of their name).

The PAR tools should place them correctly later on - though if you have occupied the "right" place with another component you will get conflicts.

Just one of the odd things Floorplanner has done since version 3.1...

- Brian

Reply to
Brian Drummond

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.