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picoblaze RS-232 using 62.5 MHz

Hi, I was currently using picoblaze with RS-232 with the FPGA running at

50 MHz and it worked fine. I now need to run it at 62.5 MHz. From the information I hve gathered, to attain a baud rate of 115200, I would need a clock frequency of 115200 * 16 = 1843200 Hz or something close to that.

In the picobalze hdl file, there is a counter that counts 27 cycle at

50 MHz to obtain 1851851 Hz and it seems to work fine with the RS-232. So I figure 33 cycles at 62.5 MHz to obtain 1893939 Hz should also work but I keep getting garbage on the terminal program on the computer. I have tried 32 cycles as well as 34 cycles without any luck.

I was wondering if anybody has tried this before and can shed some light on the matter. Thanks a lot, Amish

Reply to
axr0284
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UARTS are good for a bit of a frequency mismatch but going from .47% error to 2.75% error appears to be too much for your system to handle. Consider dividing 62.5 MHz by 34 instead to get .27% error. It shouldn't be important that 1838235 Hz is less than 1843200 Hz but that it's much closer than 1893939 Hz.

Reply to
John_H

Reply to
axr0284

Reply to
axr0284

You could try an intermediate freq, just in case your total system has hit a speed ceiling :)

Also, check the bit timing with a scope to confirm you have the numbers

right.

Some of the better UARTS support fractional baud define, where they do not always use 16 clks per bit, but can rate-multiply between 15 or 16, over the Rx bits. That gives you more Xtal freedom, and you can get closer to the precise baud rate, or higher baudrates.

-jg

Reply to
-jg

Hi,

I have used a similar approach with Ken Chapman's UARTs, where I wanted to run at 115200 baud with a 25 MHz reference clock. This particular combination has significant mismatch with an integer enable count, so I did this:

always @(posedge clk) begin if (en_16_x_startover) en_16_x_cntr

Reply to
Eric Crabill

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