Hi chaps
I'm fairly sure I can power down the IO buffers of a Coolrunner II with the internal logic powered, but I'm looking to see if anyone does this or has done it just for confirmation.
From the datasheet:
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Mixed Voltage, Power Sequencing, and Hot Plugging
As mentioned in I/O Banking, CoolRunner-II CPLD parts support mixed voltage I/O signals. It is important to assign signals to an I/O bank with the appropriate I/O voltage. Driving a high voltage into a low voltage bank can result in negative current flow through the power supply pins. The power applied to the VCCIO and VCC pins can occur in any order and the CoolRunner-II CPLD will not be damaged.
***For best results, we recommend that VCCINT be applied before VCCIO.*** This will ensure that the internal logic is correct before the I/Os are active. CoolRunner-II CPLDs can reside on boards where the board is inserted into a "live" connector (hot plugged) and the parts will be well-behaved as if powering up in a standard way.
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Highlight mine. That implies I can power (should!) the internal logic before powering the IOs, but can I do that indefinitely?
Any comments?
Cheers
PeteS