Transport Delays in Modelsim

Has anyone ever been able to get Modelsim to model transport delays in Verilog? Verilog simulators, by default, use inertial delays, so if you have an assignment such as this:

assign #4 sig_out = sig_in;

then any pulse on sig_in that is less than 4ns will get swallowed. Modeling transport delays prevents this from happening. Modelsim claims to model transport delays using the +transport_int_delay option for vsim, but this just doesn't seems to work.


Reply to
Kevin Neilson
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I think you'll find that this option applies only to interconnect delays that have been backannotated from an SDF file. The Verilog language defines continuous driver delays and net delays to be inertial, and I was under the impression that simulators aren't supposed to disobey that.

If you want transport delay in your own Verilog model, use intra-assignment nonblocking delays - try tnis...

always @(sig_in) sig_out

Reply to
Jonathan Bromley

That is wonderful. It totally works. I wish I'd known this before. My Palnitkar book makes no reference to this (unsurprisingly) that I can see though I did find a reference in a book by Bhasker. I would like to be able to adjust the delay on-the-fly, in order to model pad/trace delays that change over time, but I don't think that's possible. I suppose maybe I could get a switchable delay doing something like this:

always@(sig_in, dly_sel) sig_out

Reply to
Kevin Neilson

Lots of people say that when we tell them :-)

It can do other magic too. The #N transport delay can be replaced with an event control:

sig_out be able to adjust the delay on-the-fly, in order to model pad/trace

It's panto time... Oh yes it is!!!!

The numeric value in the delay expression is evaluated each time the statement executes; it can be any run-time expression, unlike the delay in a continuous assign which must be an elaboration-time constant. The only thing to note is that any expression needs to be enclosed in parentheses. So...


Reply to
Jonathan Bromley

This is great stuff. I replaced all of my adjustable delay lines, which consisted of long shift registers clocked by a 10GHz clock so I could achive 100ps resolution. This was slowing down the simulation drastically. I guess it is panto time--whatever that might be. -Kevin

Reply to
Kevin Neilson

Sorry, I should have taken note of your timezone.

Someone else please explain :-)

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
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Reply to
Jonathan Bromley

Perhaps this will help....

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Or maybe not!

- Brian

Reply to
Brian Drummond

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