I have a 3.3V (differential, LVPECL) clock for my MGTCLK. Are they
3.3V tolerant? Is there anyway of making this work without having to put down a level shifting buffer?Thanks, Dale
I have a 3.3V (differential, LVPECL) clock for my MGTCLK. Are they
3.3V tolerant? Is there anyway of making this work without having to put down a level shifting buffer?Thanks, Dale
Dale,
Simplest method is to use resistors to scale the voltage to the correct levels.
+out ------/\/\/\/\------+in------/\/\/\/\-----gnd-out ------/\/\/\/\----- -in-----/\/\/\/\/-----gnd
Choose the R's to drop the voltage into the acceptable range desired.
You may also need some resistance from + to - to perform the termination (or choose all the R's so that proper termination is also accomplished).
For a clock signal, you may also use capacitive coupling, but you still need to terminate the receive, and then set the correct common mode level at the receiver.
cap
+out --------||---------+in | 51 ohms | Vcommon | 51 ohms |-out --------||--------- -in cap
Aust> I have a 3.3V (differential, LVPECL) clock for my MGTCLK. Are they
Austin Lesea schrieb:
Austin: Let me quote the original poster: "I have a 3.3V (differential, LVPECL) clock for my MGTCLK. Are they
3.3V tolerant?"So the question remains: What are the correct levels for MGTCLK? The Virtex-4 Datasheet only specifies Peak-to-Peak Differential Input Voltage.
Yes, MGTCLK is a clock signal.
The UG076 uses different wording. Accordingly capacitive coupling "must be used" (Page 191).
No, you do not. UG076, Figure 6-7.
There is no common mode level specified anywhere that I can see it. Figure 6-7 suggests a circuit without external common mode setting. Maybe this is done internally, but who knows.
Please supplement the datasheet with the missing information.
Kolja Sulimma
Kolja,
see below
-snip- Sulimma wrote:
No. The IO pins are tied to the a supply through diodes, so applying any signal that exceeds that supply will forward bias the clamp diode. The common mode voltage also wants to be about 1/2 of the supply (typically, but not always, as we see below).
-snip-
Table 12,
has no common mode specifically stated for the MGT clock reference inputs.
It appears that V4 FX wants to set its own common mode, hence the reason why capacitive coupling is required. And since it has an internal termination, it makes the only specification required, the peak to peak swing (everything else is automatically taken care of).
(snip regarding 3.3v differential signals)
(I was about to jokingly suggest capacitive coupling, then I scroll down.)
I suppose for a clock, capacitive coupling works fine. It doesn't for a signal with an arbitrarily long time between transitions.
-- glen
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