Field-Programmable Gate Arrays

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crossing clock domain ??

Hi all, I have to transfert signals from a clock domain to another. First clock domain is fixed, but the second can be...
10 comments posted 19yrs
posted by matthieu.cattin
10 comments posted 19yrs posted by matthieu.cattin

Operate Flash S29GL-N from Spansion

Hi, Is there someone have the experience with using flash s29gl-n from spansion? Is it possible to enter the "Write Buff...
0 comments posted 19yrs
posted by zhongqiang.cheng
0 comments posted 19yrs posted by zhongqiang.cheng

Is the FSL a good approach for this...?

I have a piece of custom IP that recovers data from an external part. The data comes in at 312 MHz and is deserialized...
1 comments posted 19yrs
posted by mottoblatto
1 comments posted 19yrs posted by mottoblatto

PCI-Express TLP example

I need to simulate a PCI-E packet stream for a design with a correctly formed LCRC. I've found some DLLP examples but n...
3 comments posted 19yrs
posted by fred
3 comments posted 19yrs posted by fred

Delaying signal

What's the best way to delay a signal? I want a certain control signal to appear X nano seconds after the rising edge o...
2 comments posted 19yrs
posted by null
2 comments posted 19yrs posted by null

Possibility of 80188 VHDL core

I currently have several products based around the Intel 80188 microcontroller and it it soon to become obsolete. I bel...
4 comments posted 19yrs
posted by news
4 comments posted 19yrs posted by news

V4FX PPC data cache behaviour?

Hi, I'm designing the logic for a project with very slow memory. My question is about the behaviour of the PowerPC data...
0 comments posted 19yrs
posted by jetmarc
0 comments posted 19yrs posted by jetmarc

crash of xilinx fpga_editor

Hello everyone, when i wanted to delete a net in hard macro design, the fpga_editor always crashed. Does anyone know wh...
0 comments posted 19yrs
posted by lipeng.net
0 comments posted 19yrs posted by lipeng.net

Quartus II 6.1 Remove Duplicate Logic option removed

The remove duplicate logic option has been removed from Quartus II 6.1. I tried searching the manual to find which sett...
0 comments posted 19yrs
posted by Wilhelm.Klink
0 comments posted 19yrs posted by Wilhelm.Klink

Variable clock using Virtex 4?

Is there a way to create a variable clock that behaves like a VCO using the Virtex 4? If not clock, how about variable a...
2 comments posted 19yrs
posted by null
2 comments posted 19yrs posted by null

CREATE FPGA-PC CONNECTION (LWIP, XILNET)

Can anyone tell me some code to probe socket connection between PC and my Spartan 3E?. I have created projects with Xil...
0 comments posted 19yrs
posted by pbantunez
0 comments posted 19yrs posted by pbantunez

(-1)*xn operation in FPGA

Hi, in C programming,it's easy to get a negative value of any variables, as minus -xn; in FPGA, suppose it's 16bit 2's...
3 comments posted 19yrs
posted by iamsunlei
3 comments posted 19yrs posted by iamsunlei