Field-Programmable Gate Arrays

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Need help to buy first FPGA board!

Hi everyone, I am newbie in FPGA; recently I decide to buy a FPGA board to study. I am considering two boards: 1. Virte...
0 comments posted 19yrs
posted by dang_hut
0 comments posted 19yrs posted by dang_hut

Need heep to buy first FPGA board!

Hi everyone, I am newbie in FPGA; recently I decide to buy a FPGA board to study. I am considering two boards: 1. Virte...
0 comments posted 19yrs
posted by dang_hut
0 comments posted 19yrs posted by dang_hut

Structured ASIC players

NEC will exit the structured ASIC business http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=197008125 Is tha...
3 comments posted 19yrs
posted by newsgroup
3 comments posted 19yrs posted by newsgroup

internal DCM

Hi Can any body explain internal DCM and give me some information about it? Thank you
5 comments posted 19yrs
posted by saghaian
5 comments posted 19yrs posted by saghaian

2x technique

Hi Is there a technique to 2x our input clock and as a general Is there a technique to create a clock with frequency of...
3 comments posted 19yrs
posted by saghaian
3 comments posted 19yrs posted by saghaian

porting virtex2-pro into virtex4. Performance!!

Hello. I implemented floating point adder in virtex2-pro and now recomplied it in virtex4. There is no compile error in...
4 comments posted 19yrs
posted by lkjrsy
4 comments posted 19yrs posted by lkjrsy

VHDL code for Generating registers

I want to generate a program in VHDL for generating registers which can be used then into a state machine. If anyone has...
2 comments posted 19yrs
posted by sandip.gaikwad
2 comments posted 19yrs posted by sandip.gaikwad

Using Xilinx DCM FX output without DLL

I need to design an FPGA for a chip bringup system with the following clocking requirements: There is a 2.75 MHz input...
2 comments posted 19yrs
posted by dipumisc
2 comments posted 19yrs posted by dipumisc

Determine error in asynchronous signal

Hi, first of all, I know that asynchronous signals are bad, etc but that's what i have to work with. I am using Spartan...
14 comments posted 19yrs
posted by axr0284
14 comments posted 19yrs posted by axr0284

OPB IPIF: write to DIER causing bus timeout

I'm talking to an IPIF device on the OPB bus from a linux driver. My problem is that when I try to write to the DIER re...
1 comments posted 19yrs
posted by neil.steiner
1 comments posted 19yrs posted by neil.steiner

how to use STD_LOGIC_VECTOR2

Hi I need to convert type : array (0 to 3) of std_logic_vector (31 downto 0) to type : STD_LOGIC_VECTOR2 ( 3 downto 0 ,...
1 comments posted 19yrs
posted by pasacco
1 comments posted 19yrs posted by pasacco

up down lfsr

how to create an 8 bit up down lfsr
2 comments posted 19yrs
posted by jamsvlsi
2 comments posted 19yrs posted by jamsvlsi

nets vs. pads ; constraints question

Hello all, What is the difference between a NET and a PAD with regards to constraints management? Also, I noticed that...
1 comments posted 19yrs
posted by nugentoffer
1 comments posted 19yrs posted by nugentoffer