Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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nets vs. pads ; constraints question
Hello all, What is the difference between a NET and a PAD with regards to constraints management? Also, I noticed that I can constrain my FPGA_CLK but it looks like there's another element called...
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17 years ago
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Cyclone II "altsyncram" timing constraints?
Just wondered if anyone could point me to documentation on the timing constraints for the "altsyncram" standard module on Cyclone II. I have chapter 8 of the device handbook, which has a basic...
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17 years ago
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Extended CFP for CIC 2007: (submission date extended to March 9, 2007)
Extended Call for Papers Extended Submission Date: March 9, 2007 The 2007 International Conference on Communications in Computing: CIC 2007 Monte Carlo Resort hotel, in Las Vegas, Nevada, USA June 25...
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17 years ago
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newbie question
Hi While delivering an IP is it necessary to have all the outputs registered? what is the advantage from this?
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17 years ago
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RTOS?
I am developing an FPGA application which works in series with a main processor which is running an RTOS(VxWorks). Since my inputs and outputs are to and from that processor, should i be using any...
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17 years ago
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Spartan-3E Sample Packs
Does anyone have any of these things for sale? I missed out when they came out, and would love to get my hands on a couple. If anyone has any unused laying around.. please let me know..
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17 years ago
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Looking for a superscalar simulator
Hi all, before doing the hardware implementation I wanna trace the instruction buffer in a simulator for some special algorithms. Could anyone suggest me a dual-issue simulator that allows to...
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17 years ago
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PETALINUX AUTO-BOOT
Hello, I have tried to implement uclinux (from Petalogix) in a Spartan 3E. I have followed the Spartan 3E tutorial, but when I reboot my fpga, the termNo existing image in FLASH. So I program the...
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17 years ago
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Selecting device in Project Properties : no XC2V1000?
Hello, I'm new in using ISE and I'm trying to start project for Virtex2 FPGA with 1M gates - but in Project Properties (after selecting "Virtex2" in Family field) I can't find xc2v1000 as an option in...
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17 years ago
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can I convert DPRAM to SPRAM?
Hi, Is there any way of implementing DPRAM from single port RAM's?(may be by connecting two SPRAM's) Thanks
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17 years ago
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Xilinx ML402 Virtex-4 Eval kit - I2C Bus
Hello, I recently obtained a ML402 Virtex-4 SX35 evaluation board from Xilinx and would like to use it to communicate with some I2C slave devices. What is the proper way to do this? I am new to FPGA /...
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17 years ago
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Managing input clock of 20MHz at input of DCM
Hi all I have a clock of 20Mhz on my board and I want Digital clock manager to generate a clock of 130MHz in my Xilinx Virtex-2 xc2v1000 FPGA. Now , the problem is that the DCM requires atleast 24Mhz...
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17 years ago
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configuring in slave serial mode with serial platform PROM
i have a problem while configuring the virtex2 pro fpga in slave serial mode i am using platform flash RPOM of XC40FS serial flash prom. i am not getting the done pin high after configuration. my...
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17 years ago
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How to get the area/time results without IO mapping
Hi all, I want to evaluate the area and time cost of an intermediate product on Xilinx FPGA. But the number of output ports exceed number of I/O pins. (Actually there will be much less outputs in the...
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17 years ago
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Xilinx MIG DDR2 Documentation
I am trying to use the Xilinx Memory Interface Generator (MIG) version 1.6 to generate a DDR2 x16 core for initiall testing of a XC4VFX12-10SF363 board that we are bringing up this week. The memory is...
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17 years ago
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