Hi all,
I want to evaluate the area and time cost of an intermediate product on Xilinx FPGA. But the number of output ports exceed number of I/O pins. (Actually there will be much less outputs in the final product. )
But currently, I need test the intermediate product by using Xilinx ISE. Can I add some ISE specific declaration to avoid the fully IO mapping while I can still get the area and time cost reports?
Thanks a lot.
Sincerely, Aaron
Can you instantiate a Chipscope ILA (and ICON) and wire the IO up to that? That's worked for us in the past.
Or send the output ports into a big shift register and shift them out of one pin, just to persuade the SW they get used?
Cheers, Martin
-- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.html
Theoretically (i.e. I have never tried this. sorry ;)) you can use "map -u" (do not remove unused logic) with "TPSYNC" and/or "TPTHRU" contraints.
Cheers, Jim
And make sure you have the synthesis tool NOT put in IO buffers.
I do this quite often when evalutating the resource utilization of lower-level modules.
JTW
In addition to the suggestions others have already given you, you can also define an area group for the logic you want to evaluate, and the MAP and PAR reports will give you a resource utilization report for each area group that you have defined within your design.
Regards,
John McCaskill
ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.