Field-Programmable Gate Arrays

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nets vs. pads ; constraints question

Hello all, What is the difference between a NET and a PAD with regards to constraints management? Also, I noticed that...
1 comments posted 19yrs
posted by nugentoffer
1 comments posted 19yrs posted by nugentoffer

Cyclone II "altsyncram" timing constraints?

Just wondered if anyone could point me to documentation on the timing constraints for the "altsyncram" standard module...
3 comments posted 19yrs
posted by jules
3 comments posted 19yrs posted by jules

newbie question

Hi While delivering an IP is it necessary to have all the outputs registered? what is the advantage from this?
1 comments posted 19yrs
posted by bajajk
1 comments posted 19yrs posted by bajajk

RTOS?

I am developing an FPGA application which works in series with a main processor which is running an RTOS(VxWorks). Sinc...
1 comments posted 19yrs
posted by aswingopalan
1 comments posted 19yrs posted by aswingopalan

Spartan-3E Sample Packs

Does anyone have any of these things for sale? I missed out when they came out, and would love to get my hands on a coup...
0 comments posted 19yrs
posted by ziggy
0 comments posted 19yrs posted by ziggy

Looking for a superscalar simulator

Hi all, before doing the hardware implementation I wanna trace the instruction buffer in a simulator for some special a...
0 comments posted 19yrs
posted by grabherp23
0 comments posted 19yrs posted by grabherp23

PETALINUX AUTO-BOOT

Hello, I have tried to implement uclinux (from Petalogix) in a Spartan 3E. I have followed the Spartan 3E tutorial, but...
0 comments posted 19yrs
posted by pbantunez
0 comments posted 19yrs posted by pbantunez

can I convert DPRAM to SPRAM?

Hi, Is there any way of implementing DPRAM from single port RAM's?(may be by connecting two SPRAM's) Thanks
5 comments posted 19yrs
posted by bajajk
5 comments posted 19yrs posted by bajajk

Xilinx ML402 Virtex-4 Eval kit - I2C Bus

Hello, I recently obtained a ML402 Virtex-4 SX35 evaluation board from Xilinx and would like to use it to communicate w...
1 comments posted 19yrs
posted by m.afgani
1 comments posted 19yrs posted by m.afgani

Managing input clock of 20MHz at input of DCM

Hi all I have a clock of 20Mhz on my board and I want Digital clock manager to generate a clock of 130MHz in my Xilinx...
2 comments posted 19yrs
posted by moazzamhussain
2 comments posted 19yrs posted by moazzamhussain

Xilinx MIG DDR2 Documentation

I am trying to use the Xilinx Memory Interface Generator (MIG) version 1.6 to generate a DDR2 x16 core for initiall tes...
3 comments posted 19yrs
posted by widding
3 comments posted 19yrs posted by widding