Just wondered if anyone could point me to documentation on the timing constraints for the "altsyncram" standard module on Cyclone II. I have chapter 8 of the device handbook, which has a basic diagram, but when I try to duplicate the timing of this diagram, I don't seem to be able to get clock speeds above about 100MHz to work correctly (according to Quartus II's simulation). I understood this module was supposed to function at 200MHz, so I guess I must be doing something wrong, but what it is I'm at a loss to explain. I've tried shifting my clock signal's phase in relation to the control signals, but haven't found anything that helps. In case it's relevant, I'm using it in true dual-port mode, with a single clock for both ports.
16 years ago