Cyclone II "altsyncram" timing constraints?

Just wondered if anyone could point me to documentation on the timing constraints for the "altsyncram" standard module on Cyclone II. I have chapter 8 of the device handbook, which has a basic diagram, but when I try to duplicate the timing of this diagram, I don't seem to be able to get clock speeds above about 100MHz to work correctly (according to Quartus II's simulation). I understood this module was supposed to function at 200MHz, so I guess I must be doing something wrong, but what it is I'm at a loss to explain. I've tried shifting my clock signal's phase in relation to the control signals, but haven't found anything that helps. In case it's relevant, I'm using it in true dual-port mode, with a single clock for both ports.

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What speed grade part do you have? Only the fastest part is spec'd to operate its M4K (true dual port mode) at 200MHz. Other key contributors to this high memory speed are:

  1. both ports driven from the same clock (which is what you are doing).
  2. memory clocks driven by the internal PLL onto the global clock network.

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If you are using the RAM as top level in your test design maybe you should use additional input and output registers

Rgds Andre

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Hi Jules,

Using it on my board with a 2C20F484C7, no registers on the outputs, it takes around 8ns for the outputs to stabilize after the clock pulse transition.

That is using the V6.1 Q2 and libraries, according the simulation results.

Your results may vary depending on your C2's speed grade, the version of Q2 libraries you are using (if the megafunctions have changed that is), or other aspects of your design.


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