Field-Programmable Gate Arrays

Xilinx ISE webpack in Ubuntu?

Hello, I am kind of new to running linux on my own machine at home and I have chosen to use Ubuntu. I would like to run...

16 comments posted 19yrs

posted by thesteveman_ice9

16 comments posted 19yrs posted by thesteveman_ice9

Edge vs Level triggering

Hi, Appreciate if anyone could explain me the significance of edge triggering vs level triggering. I know what they are...

1 comments posted 19yrs

posted by mahenreddy

1 comments posted 19yrs posted by mahenreddy

OPB BRAM not detected in EDK

I am trying to design a system which has a BLOCK RAM on the OPB Bus , interfaced through a OPB_BRAM_IF_CNTLR. I first a...

0 comments posted 19yrs

posted by get2venu

0 comments posted 19yrs posted by get2venu

Bluetooth standard in software defined radio

hello I am a student in the faculty of engineering and i am doing my final year project and it is based on System on ch...

0 comments posted 19yrs

posted by taysonm_2001

0 comments posted 19yrs posted by taysonm_2001

Making a 32KB BRAM block, virtex-4

Hi all, I am working on making a second level cache for microbalze processor on a ML403 board. This comes in the virtex...

15 comments posted 19yrs

posted by vbhanu

15 comments posted 19yrs posted by vbhanu

Xilinx Platform cable USB and impact on linux without windrvr

Hello, after being bitten by windrvr once again (it did not compile after a kernel upgrade), I decided to see if I coul...

21 comments posted 19yrs

posted by mike

21 comments posted 19yrs posted by mike

MIG 1.6 on ISE9.1i

Hi everybody, I tried to recompile under ISE9.1.01i a project which uses MIG1.6. The MIG1.6 controller was generated un...

0 comments posted 19yrs

posted by taileb.mehdi

0 comments posted 19yrs posted by taileb.mehdi

How to specify ISE INST constraint with GENERATE statements?

I'm having trouble getting an IBUFDS to use differential termination, DIFF_TERM = "TRUE". I'm specifying the pads with:...

3 comments posted 19yrs

posted by killerhertz

3 comments posted 19yrs posted by killerhertz

Interfacing to 10Gig ethernet with Xilinx FPGAs

Hello there, I have a query for the more knowledgeable than me.. We've been playing quite successfully with 1 gig Ether...

7 comments posted 19yrs

posted by marc

7 comments posted 19yrs posted by marc

Small FPGA Dev Board with Ethernet

Does anybody know of a good, --small--, development board with an ethernet port? What I'm really looking for is essenti...

2 comments posted 19yrs

posted by chrismurf

2 comments posted 19yrs posted by chrismurf

SystemVerilog?

I've been interested in using SystemVerilog for quite some time now I don't really know if the tool support is there ye...

4 comments posted 19yrs

posted by ehliar

4 comments posted 19yrs posted by ehliar

Help for video compression

HI Every body, I hope well to help me in regards to my problem: I want to program a coding unit of video that is the on...

1 comments posted 19yrs

posted by abaidik

1 comments posted 19yrs posted by abaidik

demande aide

salut, j'espere bien m'aider en ce qui concerne mon probleme: je veux programmer un module de codage de video qui est c...

7 comments posted 19yrs

posted by abaidik

7 comments posted 19yrs posted by abaidik

Not power of two BRAM size problem

Hi Everybody, I'm using a xc2vp4 FPGA from Xilinx which has 28 blocks of 18Kb (= 504 Kb = 63 KB) of BRAM. The problem i...

3 comments posted 19yrs

posted by cispa

3 comments posted 19yrs posted by cispa

Chipscope with Spartan 3E Starter Kit

Hi, I have a project based on MicroBlaze. Everything works fine, I debug software in SDK. But now I need to check in/ou...

0 comments posted 19yrs

posted by d_domanski

0 comments posted 19yrs posted by d_domanski