Hello all,
What is the difference between a NET and a PAD with regards to constraints management?
Also, I noticed that I can constrain my FPGA_CLK but it looks like there's another element called FPGA_CLK_c . Why does Xilinx ISE add this extra element? What is it?
Thanks.
The Xilinx Constraints Guide includes the applicable elements list for each constraint. Often - but not always - an attribute attached to a NET may propagate to the PAD or pad INST that's attached to it. If you wonder whether the PAD or NET is the right target for a specific constraint, look up that constraint in the Constraints Guide.
I haven't worked much with XST but I've seen this in Synplify results often enough - when a clock pin is included in the pin list for the top module and the synthesizer recognizes it as a clock pin, a clock buffer is added by the synthesizer (rather than requiring the manual instantiation) to deliver the clock over the global clock routing network. Adding this buffer between the pad and registers means there are now two nets. Typically the net connecting the pad to the buffer will have the _c appended to the name to make the net unique but understandably related to the clock.
- John_H
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