Latest threads in Field-Programmable Gate Arraysshow only best voted threads
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XC3S400 and XC3S500E in PQ208
While both Device/package combinations are listed in the datasheets, I have not seen any of these devices "out in the wild" (means available with Digikey(*)/Nuhorizons/Avnet). I bothered Xilinx people...
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17 years ago
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Xilinx ISE webpack in Ubuntu?
Hello, I am kind of new to running linux on my own machine at home and I have chosen to use Ubuntu. I would like to run Xilinx ISE webpack if possible. On my first attempt I couldn't get the windows...
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17 years ago
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Edge vs Level triggering
Hi, Appreciate if anyone could explain me the significance of edge triggering vs level triggering. I know what they are but don't understand the significance except in interrupts. Where do we need...
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17 years ago
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OPB BRAM not detected in EDK
I am trying to design a system which has a BLOCK RAM on the OPB Bus , interfaced through a OPB_BRAM_IF_CNTLR. I first add an "opb_bram_if_cntlr_0" , and connected it as a slave on the OPB Bus . The...
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17 years ago
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Bluetooth standard in software defined radio
hello I am a student in the faculty of engineering and i am doing my final year project and it is based on System on chip. i us a development board " till now i am using cyclone kit " but i am ordeing...
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17 years ago
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Making a 32KB BRAM block, virtex-4
Hi all, I am working on making a second level cache for microbalze processor on a ML403 board. This comes in the virtex-4 family. I am looking at 32KB space for cache data. The tag stays in a separate...
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17 years ago
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Xilinx Platform cable USB and impact on linux without windrvr
Hello, after being bitten by windrvr once again (it did not compile after a kernel upgrade), I decided to see if I could get the Xilinx USB cable and impact working without a kernel module. To achieve...
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17 years ago
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MIG 1.6 on ISE9.1i
Hi everybody, I tried to recompile under ISE9.1.01i a project which uses MIG1.6. The MIG1.6 controller was generated under ISE8.1.03i. The configuration was the following: The project runed...
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17 years ago
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How to specify ISE INST constraint with GENERATE statements?
I'm having trouble getting an IBUFDS to use differential termination, DIFF_TERM = "TRUE". I'm specifying the pads with: -- more code... -- Generate components for each bit array_gen : for i in...
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17 years ago
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Interfacing to 10Gig ethernet with Xilinx FPGAs
Hello there, I have a query for the more knowledgeable than me.. We've been playing quite successfully with 1 gig Ethernet in our labs that we're getting bold and want to move to 10Gig. I was...
7
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17 years ago
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Small FPGA Dev Board with Ethernet
Does anybody know of a good, --small--, development board with an ethernet port? What I'm really looking for is essentially a FPGA, on a very small PCB, with an ethernet port and power port/headers....
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17 years ago
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SystemVerilog?
I've been interested in using SystemVerilog for quite some time now I don't really know if the tool support is there yet. XST doesn't (yet?) support SystemVerilog so I tested Precision instead....
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17 years ago
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Help for video compression
HI Every body, I hope well to help me in regards to my problem: I want to program a coding unit of video that is the one of estimation and movement compensation while using the language VHDL, I want...
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17 years ago
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demande aide
salut, j'espere bien m'aider en ce qui concerne mon probleme: je veux programmer un module de codage de video qui est celui d'estimation et compensation de mouvement en utilisant le langage VHDL , je...
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17 years ago
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Not power of two BRAM size problem
Hi Everybody, I'm using a xc2vp4 FPGA from Xilinx which has 28 blocks of 18Kb (= 504 Kb = 63 KB) of BRAM. The problem is: using EDK is only possible to allocate a power of two size (in KB) for the...
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17 years ago
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