Field-Programmable Gate Arrays

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ISE:Simulation

Hi, I have a process in my code that is decides if enable pin of a counter is high or low. When i start my simulation t...
1 comments posted 19yrs
posted by anilcelebi
1 comments posted 19yrs posted by anilcelebi

How can we know how many BRAM are used?

Hello~ I'm beginner and so looking for someone who know how to get the infomation about the number of used BRAM from re...
1 comments posted 19yrs
posted by lkjrsy
1 comments posted 19yrs posted by lkjrsy

Handel-C, multiple clock domains, and PAL library

Hi, Currently, I'm doing some experiments with multiple clock domains and Handel-C (by Celoxica). However, as far as I...
0 comments posted 19yrs
posted by pczapski
0 comments posted 19yrs posted by pczapski

Xilinx and archive of Teaching Materials

Hi, I'm looking for archive of Teaching Materials (especially, Xilinx FPGA Design Flow Workshop Materials). Those avail...
0 comments posted 19yrs
posted by pczapski
0 comments posted 19yrs posted by pczapski

Modelsim (errno = ENOSPC) error

Hey all. I dont know whats happened my Modelsim but anytime I try and do anything with it like open/close/create a proj...
2 comments posted 19yrs
posted by robquigley
2 comments posted 19yrs posted by robquigley

$recovery

Hi, I am doing FPGA design with xilinx spartan 3e. When I finished P&R, I checked the timing report. Everything is ok,...
4 comments posted 19yrs
posted by chenyong20000
4 comments posted 19yrs posted by chenyong20000

Verilog Programmer / FPGA Analyst

Verilog Programmer / FPGA Analyst Germantown, MD 20874 6 Month Contract With Potential for Extension Summary: We are se...
0 comments posted 19yrs
posted by myitrecruiter
0 comments posted 19yrs posted by myitrecruiter

Redundancy

Hi all I am working on partial reconfiguration and I am stuck. Say I have an INIT value of "8000" and I am changing it...
1 comments posted 19yrs
posted by bharadwaj.sr
1 comments posted 19yrs posted by bharadwaj.sr

OFFSET and Data Clock Skew?

Hello, I'm trying to register some data coming from an ADC at 4ns period. I currently have the following in my UCF: NET...
1 comments posted 19yrs
posted by killerhertz
1 comments posted 19yrs posted by killerhertz

Spartan-3AN

finally announced! so now can talk about them - well still not documents on Xilinx website, but hopefully they will be a...
40 comments posted 19yrs
posted by Antti.Lukats
40 comments posted 19yrs posted by Antti.Lukats

ML501 Platform Flash Configuration

Hello All, I have a Xilinx ML501 board and I want to use the Xilinx XCF32P platform flash to configure the XC5VLX50. I...
2 comments posted 19yrs
posted by pete.dudley
2 comments posted 19yrs posted by pete.dudley

Xilinx platform cable USB API?

Is there a way to access the platform cable USB from a user program (i.e., from outside the Xilinx toolchain) ? What I'...
7 comments posted 19yrs
posted by Guy.Eschemann
7 comments posted 19yrs posted by Guy.Eschemann

XC3S400 and XC3S500E in PQ208

While both Device/package combinations are listed in the datasheets, I have not seen any of these devices "out in the w...
13 comments posted 19yrs
posted by bon
13 comments posted 19yrs posted by bon