Latest threads in Field-Programmable Gate Arrays

XPS (NGCBUILD) fails when creates netlist: "failed to copy to implementation"

I created a peripheral named o2p, it is a bridge to communicate the PLB Bus with a On Chip Bus(developed in my company)...

1 19yrs

le_marq

1 19yrs le_marq

google tech talks : "General Purpose, Low Power Supercomputing Using Reconfiguration"

FYI : http://video.google.com/videoplay?docid=-4969729965240981475

0 19yrs

rponsard

0 19yrs rponsard

what about dma scatter /gather support in xilinx edk ipif ?

I have a project that need dma support and after I read some document and code in Xilinx EDK, I'm confused by dma suppo...

0 19yrs

huangjielg

0 19yrs huangjielg

Regional Clock Network and Large Designs

Hello, I'm getting usual results from my BUFR network in Timing Analyzer: ---------------------------------------------...

3 19yrs

killerhertz

3 19yrs killerhertz

Where can i get free CAN VHDL core

Hi, I am going through the net to download CAN VHDL core. HurriCANe is removed from the ESA site, and the link in openc...

4 19yrs

raju.penum

4 19yrs raju.penum

what does a 'blank check' do exactly

on lets say... a Xilinx CoolRunner 2 CPLD? I had trouble finding information on this. Using Impact. thanks!

14 19yrs

mtsukanov

14 19yrs mtsukanov

Altera Byte Blaster Cable on Linux

I'm trying to use the Altera USB Byte Blaster Cable on Linux (Scientific Linux 4.4, i.e. RHEL 4). The Programmer applic...

2 19yrs

bjrosen

2 19yrs bjrosen

Xilinx USB flatform cable length mistery ?

I've just ordered couple of these cables. To make them works with my JTAG connector, I built a little 10 inches thong a...

5 19yrs

ccon67

5 19yrs ccon67

Can write, can't read with OPB_SPI 1.00e

Hello, I have a ComBlock 1200 (comblock.com) FPGA board with a Analog Devices AD9860 MxFE interface. I'm trying to get...

1 19yrs

jshamlet

1 19yrs jshamlet

SCons build tool as an alternative to makefiles

Hello, I have been using batch files to handle the build process with a Xilinx flow for a while. Now I want to move to...

15 19yrs

prdubois

15 19yrs prdubois

Virtex 4 FX Sonet Alignment

Is there anybody in this group who has experience with V4FX MGT Sonet Alignment? The documentation is rather short on d...

6 19yrs

ksulimma

6 19yrs ksulimma

PCI-E TS1s

I'm writing the initial state machine for a PCI-Express card and am stuck at the very first hurdle. I'm using a Philips...

4 19yrs

fred

4 19yrs fred

How to implement pipeline in this case?

Hello. To improve the speed, I want to implement pipeline.But variables make me sad... For example -- input: IN1,IN2 , o...

20 19yrs

lkjrsy

20 19yrs lkjrsy

Spartan MicroBlaze

Hello, Does anyone know if there is a Spartan based uBlaze development board that has SRAM on it? Best regards, Rob

4 19yrs

robnstef

4 19yrs robnstef

[Q] Xilinx Webpack warning message "Cannot apply TIMESPEC TS_WR_CPLD"

Dear all, I am using Syplify8.5 and Xilinx Webpack 9.1 to implement a CPLD XC95144XL, Verilog simulation showed everyth...

1 19yrs

heliboy2003

1 19yrs heliboy2003

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