Edge vs Level triggering


Appreciate if anyone could explain me the significance of edge triggering vs level triggering. I know what they are but don't understand the significance except in interrupts. Where do we need edge triggering and where do we need level triggering. Is this applicable only for clock signals? or for data inputs as well? why?

Thanks in advance mr

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Edge triggered registers of flip-flops accept data at a well-defined moment, usually right before the rising clock edge. Data levels at all other moments are irrelevant. "level triggered" latches accept data for the whole time that the clock level is active and enabled..The new data is immediately available on the output.

Flip-flops and registers are really implemented as two cascaded latches, with opposite clock polarities, but this is of interest only to designers who want to get really deep into the details.

Edge-triggered registers and flip-fl> Hi,

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Peter Alfke

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