SystemVerilog?

Synplify appears to support 2 and 3. I don't find reference to 1 (interfaces) in the v8.8 reference manual in my quick glance. I've been lackluster in pursuing System Verilog myself because of the synthesis/simulation support mismatch issues I had with Verilog2001; Synplify was up to speed long before Cadence. I've seen the System Verilog check box in SynplifyPro for a while but haven't gone there yet. Since it's been a while since the option first appeared, I would have thought interfaces - one of the more attractive features of System Verilog - would be in there already but the reference manual doesn't mention it.

I would check again since SystemVerilog support is quite high on their development list (so I understand) and they are bringing out frequent updates (I just downloaded 2006a.112). Also if something doesn't work let them know, like all EDA vendors they want(need) feedback especially on new features.

Personally, I wish they would spend the same amount of effort on VHDL2006.........:-(

Hans

The following doesn't seem to work:

myinterface intf0(); foo (.intf_slave(intf0)); bar (.intf_master(intf0));

In this case Precisioin claims that it has found a black-box for myinterface. However, the following seems to work:

myinterface intf0(); foo (.intf_slave(intf0)); assign intf0.some_master_signal = something;

And the following also seems to work: myinterface intf0(); foo (.intf_slave(intf0)); bar (.intf_master(intf0)); logic workaround_dummy; assign workaround_dummy = intf0.some_master_signal;

So I guess I can continue experimenting with SystemVerilog as long as I add some dummy signal from the interface to persuade Precision to take a look at the interface specification even if no signals of the interface is actually used in the file.

(This is only my initial analysis, I just got this to work so I can't say if more advanced interface constructs will work or not.)

/Andreas

..snip

Hi Andreas,

There is a new special build 2006a1.18 which, according to our Mentor TME, has some updated SystemVerilog support. See:

Regards, Hans