Hi everybody, I tried to recompile under ISE9.1.01i a project which uses MIG1.6. The MIG1.6 controller was generated under ISE8.1.03i. The configuration was the following:
>
> FPGA :
> Target Device : xc4vlx100-ff1148
> Speed grade : -11
> Options :
> HDL : verilog
> Synthesis tool : foundation_ise
> Module name : mem_interface_top
> No of controllers : 1
>
> DCI for data : enabled
> DCI for address and control: enabled
>
> /*******************************************************/
> /* Controller 0 */
> /*******************************************************/
> Interface parameters :
> Frequency : 210
> Data width : 8
> Depth : 1
> ECC : disabled
>
> Memory configuration : DDR2 SDRAM:Components
> Part number : MT47H64M8BT-37E
>
> Other Options :
> DCM : enabled
> Add test bench : enabled
> Clocking type : Direct clocking
> ClockCapableIO(CC) : enabled
>
The project runed successfully on board when compiled using ISE8.1.01 but failed to calibrate when compiled with SIE9.1.01i. I tried post-translate simulation and it failed. I understand that in the documentation is stated that the ISE8.1.03i is required but I don't understand why the same RTL code is differently sythesized! this means that a working project on older ISE is not garanteed to work on newers? I made a small search and didn't find any documentation for successfully migrate RTL code to the new ISE.
Mehdi